Product Specs

Drawing No.：JW205100XX
Date：May 30, 2019
(35/58)
CONFIDENTIAL
© silex technology, Inc.
5.4. パワーON/OFF, リセットタイミング (Power on/off and reset timing)
Power Up Sequence
Power Down Sequence
VDDIO_GPIO1
WLAN_PWD_L
BT_PWD_L
WLAN load process
(Software)
WLAN load process
(insmod or load script)
TC
VDD33
TA
TB
TD TE
BT load process
(Software)
BT load process
(insmod or load script)
Symbols
Descriptions
Specification
Units
Min.
Max.
T
A
If VDDIO_GPIO1 connected to 1.8 V
1
－
μsec
If VDDIO_GPIO1 connected to 3.3 V
0
0
μsec
T
B
VDDIO_GPIO1 が 90%に達してから
WLAN/BT のリセット解除(De-assert)までの時間
Time from VDDIO_GPIO1 reaches 90%
to WLAN/BT reset release (De-assert).
10
－
μsec
T
C
WLAN_PWD_L=High(De-assert)から
WLAN load process を開始するまでの時間
Time from BT_PWD_L = High(De-assert)
to WLAN load process start
0
－
msec
T
D
WLAN/BT のリセットが Low(Assert)になってか
VDDIO_GPIO が OFF になるまでの時間
Time from WLAN/BT reset = Low to VDDIO_GPIO = OFF.
10
－
μsec
T
E
If VDDIO_GPIO1 connected to 1.8 V
0
－
μsec
If VDDIO_GPIO1 connected to 3.3 V
－
－
μsec