User's Manual

Drawing No.：JW202570AS
Date：June 20, 2019
(47/110)
CONFIDENTIAL
© silex technology, Inc.
SDIO 信号の配線について (SDIO signal length)
SDIO 信号は SD_CLK を基準に外部回路等遅延配線としてください。
Skew of SDIO signal lines are recommended on the host board..
SX-SDMAC-2830S/SX-SDMAC-2831S
Signals
QCA9377-3
SMT PCB
Total length
(Chip+PCB)
Difference from
SD_CLK signal
Units
SD_CLK
0.951
10.478
11.429
0
mm
SD_CMD
0.368
14.825
15.193
+3.764
mm
SD_DATA3
0.101
10.808
10.909
-0.520
mm
SD_DATA2
0.264
11.090
11.354
-0.075
mm
SD_DATA1
0.112
11.010
11.122
-0.307
mm
SD_DATA0
0.425
11.325
11.750
+0.321
mm
SX-SDMAC-2831C
Signals
QCA9377-3
SMT PCB
B2B PCB
Total length
(Chip+2PCBs)
Difference from
SD_CLK signal
Units
SD_CLK
0.951
10.478
5.897
17.326
0
mm
SD_CMD
0.368
14.825
9.629
24.822
+7.496
mm
SD_DATA3
0.101
10.808
8.958
19.867
+2.541
mm
SD_DATA2
0.264
11.090
8.287
19.641
+2.315
mm
SD_DATA1
0.112
11.010
7.616
18.738
+1.412
mm
SD_DATA0
0.425
11.325
6.946
18.696
+1.370
mm
SX-SDCAC-2830
Signals
QCA9377-3
SMT PCB
SD Card PCB
Total length
(Chip+2PCBs)
Difference from
SD_CLK signal
Units
SD_CLK
0.951
10.478
31.677
43.106
0
mm
SD_CMD
0.368
14.825
27.992
43.185
+0.079
mm
SD_DATA3
0.101
10.808
32.245
43.154
+0.048
mm
SD_DATA2
0.264
11.090
31.869
43.223
+0.117
mm
SD_DATA1
0.112
11.010
32.725
43.847
+0.741
mm
SD_DATA0
0.425
11.325
31.389
43.139
+0.033
mm
表内の各数値はモジュール上での各信号配線長を、Diff from CLK の数値は SD_CLK との配線長差を示しています。Diff from CLK の値
が”+”の場合は SD_CLK より短く、”-”の場合は SD_CLK より長くホストボード上で配線することで等遅等長配線となるようにしてくだ
さい。
The value of tables means the length of SDIO signals on the module, and Diff from CLK means the difference of each SD signal’s
length from SD_CLK. “+” means the length of SD signal should be shorter from SD_CLK, “-” means the length of SD signal should
be longer from SD_CLK on your board to equate the length of SD signals.