DATA SHEET SILICONDRIVE PC CARD SSD-PXXX(I)-3100 OVERVIEW FEATURES The SiliconDrive PC Card is an optimal time-to-market replacement for hard drives and flash cards or in host systems that require low power and scalable storage solutions. • Integrated PowerArmor and SiSMART technologies • Capacity range: 32MB to 16GB • Supports both 8-bit and 16-bit data register transfers • Supports dual-voltage 3.
REVISION HISTORY SSD-PXXX(I)-3100 DATA SHEET REVISION HISTORY Document No. Release Date Changes 3100P-08DSR February 2, 2009 3100P-05DSR May 13, 2008 SSDS04-3100P-R January 28, 2008 SSDS03-3100P-R December 11, 2007 SSDS02-3100P-R July 25, 2007 SSDS01-3100P-R February 7, 2007 SSDS00-3100P-R December 29, 2006 Updated: • "System Reliability" table and changed the name to "Reliability." • "Related Documentation" table. Added: • “Projected Operational Life Span.” Updated: • “Overview.
TABLE OF CONTENTS SSD-PXXX(I)-3100 DATA SHEET TABLE OF CONTENTS Overview .......................................................................................................................... i Features ........................................................................................................................... i Revision History..............................................................................................................II List of Figures ................................
TABLE OF CONTENTS SSD-PXXX(I)-3100 DATA SHEET Attribute Memory Description and Operation ........................................................... 23 Attribute Memory Read Operations............................................................................ 23 Attribute Memory Write Operations ............................................................................ 24 Attribute Memory Map ................................................................................................
TABLE OF CONTENTS SSD-PXXX(I)-3100 DATA SHEET Status Register........................................................................................................... 54 Command Register .................................................................................................... 55 Alternate Status Register ........................................................................................... 56 Device Control Register ........................................................................
TABLE OF CONTENTS SSD-PXXX(I)-3100 DATA SHEET Write DMA — CAh ............................................................................................... 85 Write Multiple — C5h ........................................................................................... 86 Write Sector(s) — 30h, 31h.................................................................................. 87 Write Long Sector(s) — 32h, 33h.........................................................................
LIST OF FIGURES SSD-PXXX(I)-3100 DATA SHEET LIST OF FIGURES Figure 1: Physical Dimensions......................................................................................... 1 Figure 2: Attribute and Common Memory Read Timing Diagram.................................. 17 Figure 3: Attribute and Common Memory Write Timing Diagram .................................. 18 Figure 4: I/O Access Read Timing Diagram ..................................................................
LIST OF TABLES SSD-PXXX(I)-3100 DATA SHEET LIST OF TABLES Table 1: System Performance ......................................................................................... 2 Table 2: System Power Requirements ............................................................................ 2 Table 3: Reliability............................................................................................................ 3 Table 4: Operational Life Span ........................................................
LIST OF TABLES SSD-PXXX(I)-3100 DATA SHEET Table 28: I/O Space Read Operations........................................................................... 42 Table 29: I/O Space Write Operations ........................................................................... 42 Table 30: Memory-Mapped Register Decoding ............................................................. 43 Table 31: Independent I/O Mode Register Decoding.....................................................
LIST OF TABLES SSD-PXXX(I)-3100 DATA SHEET Table 57: Read Buffer — E4h........................................................................................ 72 Table 58: Read DMA — C8h ......................................................................................... 73 Table 59: Read Multiple — C4h..................................................................................... 74 Table 60: Read Sector — 20h, 21h ...............................................................................
PHYSICAL SPECIFICATIONS SSD-PXXX(I)-3100 DATA SHEET PHYSICAL SPECIFICATIONS The SiliconDrive PC Card products are offered in a Type II form factor. See "Part Numbering" on page 96 for details regarding PC Card capacities. PHYSICAL DIMENSIONS This section provides diagrams that describe the physical dimensions for the PC Card. Figure 1: Physical Dimensions SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
PRODUCT SPECIFICATIONS SSD-PXXX(I)-3100 DATA SHEET PRODUCT SPECIFICATIONS Note: All SiliconDrive PC Card values quoted are typical at 25°C and nominal supply voltage. SYSTEM PERFORMANCE Table 1: System Performance Reset to Ready Startup Time (Typical/Maximum) Read Transfer Rate (Typical) Write Transfer Rate (Typical) Burst Transfer Rate Controller Overhead (Command to DRQ) 200ms/400ms 8MBps 6MBps 16.7MBps 2ms (maximum) SYSTEM POWER REQUIREMENTS Note: The 5V is the only operation for the 16GB capacity.
PRODUCT SPECIFICATIONS SSD-PXXX(I)-3100 DATA SHEET RELIABILITY Table 3: Reliability MTBF (@ 25ºC) Bit Error Rate 4,000,000 hours <1 non-recoverable error in 1014 bits read PROJECTED OPERATIONAL LIFE SPAN Table 4: Operational Life Span SiliconDrive Part# Capacity Service Life* GB Written per Day SSD-P16G-3100 16GB 648.7 Years @ 135.
PRODUCT SPECIFICATIONS SSD-PXXX(I)-3100 DATA SHEET PRODUCT CAPACITY SPECIFICATIONS Table 5: Product Capacity Specifications Product Capacity Capacity (Bytes) Number of Sectors Number of Number of Number Sectors/ Cylinders of Heads Track 32MB 64MB 128MB 256MB 512MB 1GB 2GB 4GB 8GB 16GB 63,872 128,128 254,208 508,928 1,019,088 2,046,240 4,098,528 8,251,488 16,514,064 32,215,680 499 1001 993 994 1011 2030 4066 8186 16,383* 16,383* 32,702,464 65,601,536 130,154,496 260,571,136 521,773,056 1,047,674,880
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET ELECTRICAL SPECIFICATION PIN ASSIGNMENTS The following table describes the SiliconDrive PC Card 50-pin IDE connector signals.
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET PC Card Pin Memory Mode PC Card I/O Mode IDE-ATA Mode PC Card Pin Memory Mode PC Card I/O Mode IDE-ATA Mode 28 A1 A1 A1 62 BVD23 SPKR#3 DASP# 29 A0 A0 A0 63 BVD1 STSCHG# PDIAG# 30 D0 D0 D0 64 1 31 D1 D1 D1 32 D2 D2 33 WP 34 GND D8 1 D8 D81 65 D91 D91 D91 D2 66 D101 D101 D101 IOIS16# IOCS16# 67 CD2# CD2# CD2# GND GND 68 GND GND GND Notes: NU = Not used 1= These signals are required only for
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET SIGNAL DESCRIPTIONS Table 8: Signal Descriptions Signal Name Pin A10-A0 8, 10, 11, I 12, 14, 15, 16, 17, 18, 19, 20 These address lines along with the -REG signal are used to select the following: 18, 19, 20 I In true IDE mode, only A[2:0] are used to select the one of eight registers in the Task File. The remaining address lines should be grounded by the host.
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET Table 8: Signal Descriptions (Continued) Signal Name Pin Type Description -SPKR (PC Card I/O mode) -DASP (True IDE mode) -CD1, -CD2 26, 25 (PC Card memory mode) -CD1, -CD2 (PC Card I/O Mode) -CD1, -CD2 (True IDE mode) -CE1, -CE2 7, 32 (PC Card memory mode) Card Enable O This line is the Binary Audio output from the card. If the Card does not support the Binary Audio function, this line should be held negated.
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET Table 8: Signal Descriptions (Continued) Signal Name Pin Type Description -CE1, -CE2 (PC Card I/O mode) Card Enable -CS0, -CS1 (True IDE mode) -CSEL 39 (PC Card memory mode) I -CSEL (PC Card I/O mode) -CSEL (True IDE mode) This signal is the same as the PC Card Memory Mode signal. See "I/O Space Read Operations" on page 42 and "I/O Space Write Operations" on page 42.
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET Table 8: Signal Descriptions (Continued) Signal Name Pin Type Description DMARQ (True IDE mode) 43 O D15-D00 31, 30, 29, I/O (PC Card memory 28, 27, 49, 48, 47, 6, mode) 5, 4, 3, 2, 23, 22, 21 D15-D00 (PC Card I/O mode) D15-D00 (True IDE mode) GND 1, 50 (PC Card memory mode) GND (PC Card I/O mode) GND (True IDE mode) - In true IDE mode, this signal is used for DMA transfers between the host and device.
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET Table 8: Signal Descriptions (Continued) Signal Name Pin -IORD 34 (PC Card memory mode) -IORD (PC Card I/O mode) Type Description I This is an I/O read strobe generated by the host. This signal gates I/O data onto the bus from the SiliconDrive CF when the card is configured to use the I/O interface. In true IDE mode, this signal has the same function as the PC Card I/O mode.
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET Table 8: Signal Descriptions (Continued) Signal Name Pin -ATA SEL (True IDE mode) -RDY/-BSY 37 (PC Card memory mode) Type Description To enable true IDE mode, this input should be grounded by the host. O In memory mode, this signal is: • Set high when the SiliconDrive CF is ready to accept a new data transfer operation. • Held low when the card is busy. The host memory card socket must provide a pull-up resistor.
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET Table 8: Signal Descriptions (Continued) Signal Name Pin -REG 44 (PC Card memory mode) Attribute Memory Select Type Description I This signal is used during memory cycles to distinguish between common memory and register (attribute) memory accesses. This signal is set: • High for common memory. • Low for attribute memory. The signal must also be active (low) during I/O cycles when the I/O address is on the bus.
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET Table 8: Signal Descriptions (Continued) Signal Name Pin Type Description VCC This signal is the same for all modes. (PC Card I/O mode) VCC This signal is the same for all modes. (True IDE mode) -VS1, -VS2 33, 40 -VS1, -VS2 (PC Card I/O mode) -VS1, -VS2 (True IDE mode) -WAIT 42 (PC Card memory mode) -WAIT (PC Card I/O mode) -IORDY (True IDE mode) -WE 36 (PC Card memory mode) O Voltage Sense Signals.
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET Table 8: Signal Descriptions (Continued) Signal Name Pin Type Description -WE (True IDE mode) In true IDE mode, this input signal is not used and should be connected to VCC by the host. WP 24 (PC Card memory mode) O -IOIS16 (PC Card I/O mode) -IOIS16 (True IDE mode) Write Protect Memory Mode. The SiliconDrive CF does not have a write protect switch. This signal is held low after the completion of the reset initialization sequence.
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET CAPACITANCE Table 10: Capacitance Symbol Parameter Maximum Units Cin Input Capacitance 35 pF Cout Output Capacitance 35 pF CI/O Bidirectional Capacitance 35 pF DC CHARACTERISTICS Table 11: DC Characteristics 3.3 V ±10% Symbol Parameter 5V ±10% Units Minimum Maximum Minimum Maximum VCC ILI ILO VCCR VCCW VCCS VIL VIH VOL VOH Power Supply 3.0 Voltage Input Leakage *(1) Current Output Leakage *(1) Current 3.6 4.5 5.
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET AC CHARACTERISTICS Attribute and Common Memory Read Timing tRC tGHAX tA(A) ____ A[10::0],REG tA(CE) tAXQX tELWL __ CE tAVWL __ OE tGHEH tA(OE) tDIS(OE) tEN(OE) D[15::0] Figure 2: Attribute and Common Memory Read Timing Diagram Table 12: Attribute and Common Memory Read Timing Symbol Parameter Minimum Maximum Units tRC Read Cycle Time 100 - ns tA(A) Address Access Time - 100 ns tA(CE) Card Enable Access Time - 100 ns tA(OE
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET Attribute and Common Memory Write Timing tWR ____ A[10::0],REG tELWH tELWL __ CE tGHEH tAVWH __ OE tWLWH tAVWL tWHAX ___ WE tWHOL tWLOL tDVWH tWHDX D[15:0](Dout) tOLWH tWLQZ tOHDX tWHOX D[15:0](Dout) Figure 3: Attribute and Common Memory Write Timing Diagram Table 13: Attribute and Common Memory Write Timing Symbol Parameter Minimum Maximum Units tWR Write Cycle Time 100 - ns tWLWH Write Pulse Width 60 - ns tAVWL Address
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET I/O Access Read Timing A[10::0] tGHAX tRLIGL ____ REG tRHIGH tCLIGL __ CE tCHIGH tIGLIGH ___ IORD tIGHINH tAVIGL ______ INPACK tIGLINL ______ IOIS16 tAXISH tAVISL tIGHQX tDVRL D[15::0] Figure 4: I/O Access Read Timing Diagram Table 14: I/O Access Read Timing Symbol Parameter Minimum Maximum Units tDVRL Data Delay after IORD - 50 ns tIGHQX Data Hold following IORD 5 - ns tIGLIGH IORD Pulse Width 65 - ns tAVIGL Addres
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET I/O Access Write Timing A[10::0] tAXIGH tRLIGL ____ REG tRHIGH tCHIGH tCLIGL __ CE tIGLIGH _____ IOWR tAVIGL ______ IOIS16 tAXISH tAVISL tIGHQX tIGHDX D[15::0] Figure 5: I/O Access Write Timing Diagram Table 15: I/O Access Write Timing Symbol Parameter Minimum Maximum Units tIGHDX Data Hold following IOWR 5 - ns tIGHQX Data Setup before IOWR 20 - ns tIGLIGH IOWR Pulse Width 65 - ns tAVIGL Address Setup before IOWR 25
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET True IDE Read/Write Access Timing tICL ADDRESS Valid CS0, CS1, DA[2::0] tAVRWL tAX16H tAXRWH tRWPW ____ _____ DIOR,DIOW tDVWL WRITE DD[15::00] tDXWH READ DD[15::00] tDVRL tIOST IORDY ______ IOIS16 tDXRH tIOPW tAV16L Figure 6: True IDE Read/Write Access Timing Diagram Table 16: True IDE Read/Write Access Timing Symbol Parameter Minimum Maximum Units tICL Cycle Time 100 - ns tAVRWL Address Valid to DIOR,DIOW Setup Time 15 - ns tRWPW
ELECTRICAL SPECIFICATION SSD-PXXX(I)-3100 DATA SHEET True IDE Multiword DMA Read/Write Access Timing This function does not apply to SiliconDrives that have DMA disabled.
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET ATTRIBUTE MEMORY DESCRIPTION AND OPERATION The attribute memory plane can be read or written to by asserting the REG# signal, qualified by the appropriate combination of CE1#, OE#, and WE#. An attribute memory map describing the type and location of the information maintained in the attribute memory plane is provided in "Attribute Memory Map" on page 25.
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET ATTRIBUTE MEMORY WRITE OPERATIONS Attribute memory write operations are enabled by asserting REG#, WE#, and CE1# low. Odd byte write operations from the attribute memory plane are not valid.
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET ATTRIBUTE MEMORY MAP As stated earlier, the Attribute Memory plane is comprised of two components, the CIS and the FCRs. The following tables detail the type, location, and read/ write requirements for each of the four FCRs maintained in the attribute memory plane.
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET CARD INFORMATION STRUCTURE The CIS is data that describes the SiliconDrive CF, and is described by the CFA standard. This information can be used by the host system to determine a number of things about the Card that has been inserted. For information regarding the exact nature of this data and how to design the host software to interpret it, refer to the PC Card Standard Metaformat Specification.
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET Table 21: Card Information Structure (Continued) Attribute Data Offset 7 6 5 4 3 2 1 0 Description of Contents CIS Function 2Eh 04h TPLFID_FUNCTION = 04H Disk function, which may be silicon or removable PC Card function code 30h 01h Reserved • • System initialization byte 32h 22h R P CISTPL_FUNCE 34h 02h 36h 01h TPL_LINK 38h 01h Disk Interface Type 3Ah 22h CISTPL_FUNCE 3Ch 03h TPL_LINK 3Eh 02h 4
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET Table 21: Card Information Structure (Continued) Attribute Data Offset 7 6 56h I D C0h R 5 4 3 2 1 0 Description of Contents Configuration index 58h C0h W P B 5Ah A1h M MS IR IO Memory-mapped I/O configuration Interface Type T P I = 1: Interface byte follows D = 1: Default entry Configuration index = 0 • • • • • W = 0: Wait not used R = 1: Ready active P = 0: WP used B = 0: BVD1 and BVD2 not used IF type =
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET Table 21: Card Information Structure (Continued) Attribute Data Offset 7 6 5 4 3 2 70h I D IR IQ T P 72h 00h 01h M MS IR IO T 1 0 Description of Contents - P - Memory-mapped I/O configuration I = 0: No interface byte D = 0: No default entry Configuration index = 0 • • M = 0: No miscellaneous information Feature selection byte MS = 00: No memory space information TPCE_FS IR = 0: No interrupt information present
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET Table 21: Card Information Structure (Continued) Attribute Data Offset 7 6 5 4 3 86h R DI PI AI SI HV LV NV Nominal voltage only follows 27h 2 1 0 Description of Contents • • • • • • • • 88h 55h X Mantissa Exponent R: Reserved DI: Powerdown current information PI: Peak current information AI: Average current information SI: Static current information HV: Maximum voltage information LV: Minimum voltage information N
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET Table 21: Card Information Structure (Continued) Attribute Data Offset 7 5 4 3 2 A0h M MS IR IO T P 01h 6 1 0 Description of Contents - • • • • • • A2h 21h R DI PI AI M = 0: No miscellaneous information Feature selection byte TPCE_FS MS = 00: No memory space information IR = 0: No interrupt information present IO = 0: No I/O port information present T = 0: No timing information present P = 1: VCC only information
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET Table 21: Card Information Structure (Continued) Attribute Data Offset 7 B6h 55h X Mantissa Exponent Nominal voltage = 5V VCC nominal value B8h 4Dh X Mantissa Exponent VCC nominal 4.5V VCC minimum value BAh 5Dh X Mantissa Exponent VCC nominal 5.
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET Table 21: Card Information Structure (Continued) Attribute Data Offset 7 5 4 3 2 DAh M MS IR IO T P 21h 6 1 0 Description of Contents - • • • • • • DCh B5h R DI PI AI X DEh 1Eh E0h 4Dh Mantissa Extension E2h 1Bh CISTPL_TABLE_ENTRY E4h 12h TPL_LINK E6h C3h M MS IR IO Exponent T P - Nominal voltage = 3.
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET Table 21: Card Information Structure (Continued) Attribute Data Offset 7 6 5 4 3 ECh R DI PI AI SI HV LV NV Nominal voltage only follows 27h 2 1 0 Description of Contents • • • • • • • • R: Reserved DI: Powerdown current information PI: Peak current information AI: Average current information SI: Static current information HV: Maximum voltage information LV: Minimum voltage information NV: Nominal voltage information
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET Table 21: Card Information Structure (Continued) Attribute Data Offset 7 6 10Eh I D 110h 03h 01h 5 4 3 2 1 0 Description of Contents Configuration Index M MS IR IO T P - ATA primary I/O mapped configuration I = 0: No interface byte D = 0: No default entry Configuration index = 2 • • M = 0: No miscellaneous information Feature selection byte TPCE_FS MS = 00: No memory space information IR = 0: No interrupt informa
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET Table 21: Card Information Structure (Continued) Attribute Data Offset 7 6 5 4 3 2 1 0 Description of Contents CIS Function 13Ch 4Fh - O - 13Eh 4Eh - N - 140h 53h - S - 142h 59h - Y - 144h 53h - S - 146h 54h - T - 45h - E - 4Dh - M - 14Ah 14Ch 53h - S - 14Eh 00h - Space - 150h 56h - V - 152h 45h - E - 154h 52h - R - 156h 32h - 2 - 158h 2Eh - - - 15Ah 30
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET CONFIGURATION OPTION REGISTER (200H) The Configuration Option register is used to configure the SiliconDrive CF, define the address decoding, and initiate the software RESET sequence.
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET CONFIGURATION AND STATUS REGISTER (202H) The Configuration and Status Register (CSR) informs the host of any status changes with regard to power-down.
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET PIN PLACEMENT REGISTER (204H) Table 24: Pin Placement Register (204h) Operation D7 D6 D5 D4 D3 D2 D1 D0 Read/ Write Default Value CBVD1 CBVD2 CRDY CWProt RBVD1 RBVD2 RRDY RWProt Bit(s) Description CRDY Indicates a bit change in the RRDY (D1) bit. CWProt RRDY Indicates a bit change in the RWProt (D0) bit.
ATTRIBUTE MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET SOCKET AND COPY REGISTER (206H) Table 25: Socket and Copy Register (206h) D7 Operation Read/Write Default Value RFU 0 D6 D5 D4 D3 Copy Number 0 0 0 0 D2 D1 Socket Number 0 0 D0 0 Bit(s) Description RFU Copy Number Reserved for future use. Indicates the card number. Allows the host to differentiate between identical cards by writing to the bit of the card that is being accessed.
COMMON MEMORY DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET COMMON MEMORY DESCRIPTION AND OPERATION Common memory space can be accessed when the SiliconDrive is configured in memory-mapped mode. COMMON MEMORY READ OPERATIONS Common memory read operations are issued by asserting CE1#, CE2#, or both, and OE# low, REG#, and WE# must be inactive.
I/O SPACE DESCRIPTION AND OPERATION SSD-PXXX(I)-3100 DATA SHEET I/O SPACE DESCRIPTION AND OPERATION I/O SPACE READ OPERATIONS Table 28: I/O Space Read Operations Function Mode REG# CE1# CE2# A0 IORD# IOWR# D[15:8] D[7:0] Standby Byte Access X L L L L L Word Access I/O Inhibit Odd Byte Only Access X L L L H L H L L L X H H H H L X L X L H L X X X H H H H H High-Z High-Z High-Z Odd High-Z Odd High-Z Even Odd Even High-Z High-Z I/O SPACE WRITE OPERATIONS Table 29: I/O Space Write Operations Funct
ATA AND TRUE IDE REGISTER DECODING SSD-PXXX(I)-3100 DATA SHEET ATA AND TRUE IDE REGISTER DECODING SiliconDrive can be configured as either a a memory-mapped or an an I/O devices. As noted earlier, communication to and from the drive is accomplished using the ATA Command Block. MEMORY-MAPPED REGISTER DECODING In memory-mapped mode, the SiliconDrive registers are accessed via standard memory references (i.e., OE# and WE#).
ATA AND TRUE IDE REGISTER DECODING SSD-PXXX(I)-3100 DATA SHEET INDEPENDENT I/O MODE REGISTER DECODING Independent I/O mode or contiguous I/O mode requires the host to decode a continuous block of 16 I/O registers to select the SiliconDrive.
ATA AND TRUE IDE REGISTER DECODING SSD-PXXX(I)-3100 DATA SHEET PRIMARY AND SECONDARY I/O MAPPED REGISTER DECODING Table 32: Primary and Secondary I/O Mapped Register Decoding Reg# A10 A9:A4 A9:A4 A3 A2 A1 A0 IORD# = L Primary Secondary 0 X 1Fxh 17xh 0 0 0 0 0 0 X X 1Fxh 1Fxh 17xh 17xh 0 0 0 0 0 1 1 0 0 X 1Fxh 17xh 0 0 1 1 0 X 1Fxh 17xh 0 1 0 0 0 X 1Fxh 17xh 0 1 0 1 0 0 0 X X X 1Fxh 1Fxh 3Fxh 17xh 17xh 37xh 0 0 0 1 1 1 1 1 1 0 1 0 0 X 3Fxh 37xh 0 1 1
ATA AND TRUE IDE REGISTER DECODING SSD-PXXX(I)-3100 DATA SHEET TASK FILE REGISTER SPECIFICATION The Task File registers are used for reading and writing the storage data in the SiliconDrive. The decoded addresses are as shown in the following table.
ATA REGISTERS SSD-PXXX(I)-3100 DATA SHEET ATA REGISTERS DATA REGISTER The Data register is a 16-bit register used to transfer data blocks between the host and drive buffers. The register may set to 8-bit mode by using the Set Features Command defined in "Seek — 7Xh" on page 78. ERROR REGISTER The Error register contains the error status, if any, generated from the last executed ATA command. The contents are qualified by the ERR bit being set in "Status Register" on page 54.
ATA REGISTERS SSD-PXXX(I)-3100 DATA SHEET FEATURE REGISTER The Feature register is command-specific and used to enable and disable interface features. This register supports only either odd or even byte data transfers. Table 35: Feature Register Operation D7 D6 D5 Read/Write D4 D3 D2 D1 D0 Feature Byte SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.
ATA REGISTERS SSD-PXXX(I)-3100 DATA SHEET SECTOR COUNT REGISTER The Sector Count register is used to read or write the sector count of the data for which an ATA transfer has been made. Table 36: Sector Count Register Operation D7 D6 D5 Read/Write Default Value D4 D3 D2 D1 D0 0 0 1 Sector Count 0 0 0 0 0 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
ATA REGISTERS SSD-PXXX(I)-3100 DATA SHEET SECTOR NUMBER REGISTER The Sector Number register is set by the host to specify the starting sector number associated with the next ATA command to be executed. Following a qualified ATA command sequence, the device sets the register value to the last sector read or written as a result of the previous AT command.
ATA REGISTERS SSD-PXXX(I)-3100 DATA SHEET CYLINDER LOW REGISTER The Cylinder Low register is set by the host to specify the cylinder number low byte. Following an ATA command, the content of the register is written by the device, identifying the cylinder number low byte. In LBA mode, the 8-bit register maintains the contents of the Logical Block number address bits A15:A08.
ATA REGISTERS SSD-PXXX(I)-3100 DATA SHEET CYLINDER HIGH REGISTER The Cylinder High register is set by the host to specify the cylinder number high byte. Following an ATA command, the content of the register is set internally by the device, identifying the cylinder number high byte. In LBA mode, the 8-bit register maintains the contents of the Logical Block number address bits A23:A16.
ATA REGISTERS SSD-PXXX(I)-3100 DATA SHEET DRIVE/HEAD REGISTER The Drive/Head register is used by the host and the device to select the type of addressing (CHS or LBA), the drive letter, and either bits 3-0 of the head number in CHS mode or logical block number bits 27-24 in LBA mode.
ATA REGISTERS SSD-PXXX(I)-3100 DATA SHEET STATUS REGISTER The Status register provides the device’s current status to the host. The status register is an 8-bit read-only register. When the contents of the register are read by the host, the IREQ# bit is cleared. Table 41: Status Register Operation D7 D6 D5 D4 D3 D2 D1 D0 Read/Write BSY DRDY DWF DSC DRQ CORR IDX ERR 0 0 0 0 0 0 0 0 Default Value Bit(s) Description 7 Busy (BSY).
ATA REGISTERS SSD-PXXX(I)-3100 DATA SHEET COMMAND REGISTER The Command register specifies the ATA command code being issued to the drive by the host. Execution of the command begins immediately following the issuance of the command register code by the host. Table 42: Command Register Operation Read/Write D7 D6 D5 D4 D3 D2 D1 D0 ATA Command Code See "ATA Command Block and Set Description" on page 59 for a listing of the supported ATA commands.
ATA REGISTERS SSD-PXXX(I)-3100 DATA SHEET ALTERNATE STATUS REGISTER The Alternate Status register is a read-only register indicating the status of the device, following the previous ATA command. See "Status Register" on page 54 for specific details.
ATA REGISTERS SSD-PXXX(I)-3100 DATA SHEET DEVICE CONTROL REGISTER The Device Control register is used to control the interrupt request and issue ATA software resets. Table 44: Device Control Register Operation Write D7 D6 D5 D4 D3 D2 D1 D0 - - - - 1 SRST nIEN 0 Bit(s) Description 7-4 Reserved bits. 3 2 1 Always set to 1. Software Reset (SRST). When set, resets the ATA software. Interrupt Enable (nIEN). When set, device interrupts are disabled.
ATA REGISTERS SSD-PXXX(I)-3100 DATA SHEET DEVICE ADDRESS REGISTER The Device Address register is used to maintain compatibility with ATA disk drive interfaces. Table 45: Device Address Register Operation D7 Read/Write - Default Value 0 D6 D5 D4 D3 D2 D1 D0 nWTG nHS3 nHS2 nHS1 nHS0 nDS1 nDS0 0 1 1 1 1 1 0 Bit(s) Description 7 6 5-2 Reserved bit. Write Gate (nWTG). Low when a write to the device is in process. nHS3 to nHS0. The negated binary address of the currently selected head.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION In accordance with the ANSI ATA Specification, the device implements seven registers that are used to transfer instructions to the device by the host. These commands follow the ANSI standard ATA protocol. A description of the ATA command block is provided in the following table.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Table 47: ATA Command Set (Continued) Class Command Name Command Code FR 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 3 3 22h, 23h 20h, 21h 40h, 41h 1Xh 03h 7Xh EFh C6h 99h, E6h 96h, E2h 94h, E0h 87h F5h E8h CAh 32h, 33h C5h CDh 2 2 3 Read Long Sector Read Sector(s) Read Verify Sector(s) Recalibrate Request Sense Seek Set Features Set Multiple Mode Set Sleep Mode Standby Standby Immediate Translate Sector Wear Level Write Buffer Write DMA* Write Lo
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Check Power Mode — 98h, E5h The Check Power Mode command verifies the device’s current power mode. When the device is configured for standby mode or is entering or exiting standby, the BSY bit is set, the Sector Count register set to 00h, and the BSY bit is cleared. In idle mode, BSY is set and the Sector Count register is set to FFh. The BSY bit is then cleared and an interrupt is issued.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Executive Drive Diagnostic — 90h The Executive Drive Diagnostic performs an internal read write diagnostic test using (AA55h and 55AAh). If an error is detected in the read/write buffer, the Error register reports the appropriate diagnostic code.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Format Track — 50h The Format Track command formats the common solid-state memory array.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Identify Drive — ECh Issued by the host, the Identify Drive command provides 256 bytes of drive attribute data (i.e., sector size, count, and so on) The identify drive data structure is detailed in the following table.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Identify Drive — Drive Attribute Data Table 52: Identify Drive — Drive Attribute Data Word Data Default Address 0 1 2 3 4 5 6 7-8 9 10-19 Bytes Data Description 044Ah (fixed 2 ID bit) in IDE mode 848A (removable ID bit) in PCMCIA memory and I/ O modes XXXXh 0000h 00XXh 0000h XXXXh XXXXh XXXXh 0000h XXXXh 2 2 2 2 2 2 4 2 20 General configuration bit information • 15: Non-magnetic disk • 14: Formatting speed latency permissible gap need
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Table 52: Identify Drive — Drive Attribute Data (Continued) Word Data Default Address Bytes Data Description 20 2 0002h 21 22 0002h 0004h 2 2 23-26 27-46 47 XXXXh XXXXh 0001h 8 40 2 48 49 0000h 0002h 2 2 50 51 52 53 0000h 0100h 0000h 0000h 2 2 2 2 54 55 56 57-58 59 XXXXh XXXXh XXXXh XXXXh 010Xh 2 2 2 4 2 60-61 XXXXh 4 62 0000h 2 Buffer type • 0000h: Not specified • 0001h: A single-ported, single-sector buffer • 000
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Table 52: Identify Drive — Drive Attribute Data (Continued) Word Data Default Address Bytes Data Description 63 64 65 0407h 0003h 0078h 2 2 2 66 0078h 2 67 0078h 2 68 0078h 2 69-127 0000h 128-159 0000h 160-255 0000h 118 64 192 Multiword DMA modes supported PIO modes supported Minimum DMA transfer cycle time per word (ns) Manufacturer’s recommended DMA transfer cycle time (ns) Minimum PIO transfer cycle time without flow cont
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Idle — 97h, E3h When issued by the host, the device’s internal controller sets the BSY bit, enters the Idle mode, clears the BSY bit, and generates an interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5ms, and the automatic power-down mode is enabled. If the sector count is zero, the automatic power-down mode is disabled.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Idle Immediate — 95h, E1h When issued by the host, the device’s internal controller sets the BSY bit, enters Idle Mode, clears the BSY bit, and issues an interrupt. The interrupt is issued whether or not the Idle mode is fully entered.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Initialize Drive Parameters — 91h Initialize Drive Parameters allows the host to set the sector counts per track and the head counts per cylinder to 1 Fixed. Upon issuance of the command, the device sets the BSY bit and associated parameters, clears the BSY bit, and issues an interrupt.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Recalibrate — 1Xh The Recalibrate command sets the cylinder low and high, head number to 0h, and sector number to 1h in CHS mode. In LBA mode (i.e., LBA = 1), the sector number is set to 0h.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Read Buffer — E4h The Read Buffer command allows the host to read the contents of the sector buffer. When issued, the device sets the BSY bit and sets up the sector buffer data in preparation for the read operation. When the data is ready, the DRQ bit is set and the BSY bit in the Status register are set and cleared, respectively.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Read DMA — C8h The Read DMA command allows the host to read data using the DMA transfer protocol. Note: This function does not apply to SiliconDrives that have DMA disabled.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Read Multiple — C4h The Read Multiple command executes similarly to the Read Sector command, with the exception that interrupts are issued only when a block containing the counts of sectors defined by the Set Multiple command is transferred.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Read Sector — 20h, 21h The Read Sector command allows the host to read sectors 1 to 256 as specified in the Sector Count register. If the sector count is set to 0h, all 256 sectors of data are made available. When the command code is issued and the first sector of data has been transferred to the buffer, the DRQ bit is set.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Read Long Sector(s) — 22h, 23h The Read Long Sector(s) command operates similarly to the Read Sector(s) command, with the exception that it transfers requested data sectors and ECC data. The long instruction ECC byte transfer for Long commands is a byte transfer at a fixed length of 4 bytes.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Read Verify Sector(s) — 40h, 41h The Read Verify Sector(s) command operates similarly to the Read Sector(s) command, with the exception that is does not set the DRQ bit and does not transfer data to the host. When the requested sectors are verified, the onboard controller clears the BSY bit and issues an interrupt.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Seek — 7Xh The Seek command seeks and picks up the head to the tracks specified in the task file. When the command is issued, the solid-state memory chips do not need to be formatted. After an appropriate amount of time, the DSC bit is set.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Set Features — EFh The Set Features command allows the host to configure the feature set of the device according to the attributes listed in Table 65.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Set Multiple Mode — C6h The Set Multiple Mode command allows the host to access the drive via Read Multiple and Write Multiple ATA commands. Additionally, the command sets the block count (i.e., the number of sectors within the block) for the Read/Write Multiple command. The sector count per block is set in the Sector Count register.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Set Sleep Mode — 99h, E6h The Set Sleep Mode command allows the host to set the device in sleep mode. When the onboard controller transitions to sleep mode, it clears the BSY bit and issues an interrupt. The device interface then becomes inactive. Sleep mode can be exited by issuing either a hardware or software reset.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Standby — 96h, E2h When the Standby command is issued by the host, it transitions the device into standby mode. If the Sector Count register is set to a value other than 0h, the Auto Powerdown function is enabled and the device returns to Idle mode.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Standby Immediate — 94h, E0h When the Standby Immediate command is issued by the host, it transitions the device into standby mode.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Write Buffer — E8h The Write Buffer command allows the host to rewrite the contents of the 512- byte data buffer with the wanted data.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Write DMA — CAh The Write DMA command allows the host to write data using the DMA transfer protocol. Note: This function does not apply to SiliconDrives that have DMA disabled.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Write Multiple — C5h The Write Multiple command operates in the same manner as the Write Sector command. When issued, the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors. The DRQ bit is set at the beginning of a block transfer.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Write Sector(s) — 30h, 31h The Write Sector(s) command writes from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. When issued, the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors. The DRQ bit is set at the beginning of a block transfer.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Write Long Sector(s) — 32h, 33h The Write Long Sector(s) command operates in the same manner as the Write Sector command — when issued, the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors. The DRQ bit is set at the beginning of a block transfer.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Erase Sector(s) — C0h The Erase Sector(s) command is issued prior to the issuance of a Write Sector(s) or Write Multiple w/o Erase command.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Request Sense — 03h The Request Sense command identifies the extended error codes generated by the preceding ATA command. The Request Sense command must be issued immediately following the detection of an error via the Error register.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Translate Sector — 87h The Translate Sector command is not currently supported by the SiliconSystems’ SiliconDrive. If the host issues this command, the device responds with 0x00h in the data register.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Wear-Level — F5h The Wear-Level command is supported as an NOP command for the purposes of backward compatibility with the ANSI AT attachment standard. This command sets the Sector Count register to 0x00h.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Write Multiple w/o Erase — CDh The Write Multiple w/o Erase command functions identically to the Write Multiple command, with the exception that the implied pre-erase (i.e., Erase Sector(s) command) is not issued prior to writing the sectors.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Write Sector(s) w/o Erase — 38h The Write Sector(s) w/o Erase command functions similar to the Write Sector command, with the exception that the implied pre-erase (i.e., Erase Sector(s) command) is not issued prior to writing the sectors.
ATA COMMAND BLOCK AND SET DESCRIPTION SSD-PXXX(I)-3100 DATA SHEET Write Verify — 3Ch The Write Verify command verifies each sector immediately after it is written. This command performs identically to the Write Sector(s) command, with the added feature of verifying each sector written.
SALES AND SUPPORT SSD-PXXX(I)-3100 DATA SHEET SALES AND SUPPORT To order or obtain information on pricing and delivery, contact your SiliconSystems Sales Representative. PART NUMBERING NOMENCLATURE The following table defines the SiliconDrive PC Card part numbering scheme.
PART NUMBERING SSD-PXXX(I)-3100 DATA SHEET PART NUMBERS The following table lists the SiliconDrive’s part numbers. Table 84: Part Numbers Part Number Capacity SSD-P16G(I)-3100 SSD-P08G(I)-3100 SSD-P04G(I)-3100 SSD-P02G(I)-3100 SSD-P01G(I)-3100 SSD-P51M(I)-3100 SSD-P25M(I)-3100 SSD-P12M(I)-3100 SSD-P64M(I)-3100 SSD-P32M(I)-3100 16GB 8GB 4GB 2GB 1GB 512MB 256MB 128MB 64MB 32MB SAMPLE LABEL Standard Back Label with Lot Code Information Front Label SiliconSystems, Inc.
RELATED DOCUMENTATION SSD-PXXX(I)-3100 DATA SHEET RELATED DOCUMENTATION For more information, visit www.siliconsystems.com or contact your SiliconSystems Sales Representative. Table 85: Related Documentation SiliconDrive Application-Specific Description Technology Document Number PowerArmor SiSMART SiProtect Eliminates drive corruption. WP-007-0xR Calculates remaining useful life.WP-008-0xR Protection software for WP-003-0xR password-required, read/write, or read-only access.
