User's Manual

Bluegiga Technologies Oy
Page 31 of 52
14.2.4 PCM Timing Information
Symbol Min Typ Max Unit
128
256
512
48MHz DDS generation.
Frequency selection is
programmable.
2.9 - -
--8-kHz
f
mclkh
(a)
PCM_CLK high 4MHz DDS generation 980 - - ns
f
mclkl
(a)
PCM_CLK low 4MHz DDS generation 730 - - ns
- PCM_CLK jitter 48MHz DDS generation - - 21 ns pk-pk
PCM_SYNC frequency for SCO connection
kHz
Parameter
f
mclk
PCM_CLK
Frequency
4MHz DDS generation.
Ffrequency selection is
programmable.
--
Table 14: PCM Master Timing
(a) Assumes normal system clock operation. Figures vary during low-power modes, when system speeds
are reduced.
Symbol Min Typ Max Unit
4MHz DDS generation.
--20
48MHz DDS generation - - 40.83
t
dmclkpout
--20
4MHz DDS generation - - 20
48MHz DDS generation - - 40.83
t
dmclklpoutz
--20
t
dmclkhpoutz
--20
t
supinclkl
20 - -
t
hpinclkl
0- -
Delay time from PCM_CLK low to PCM_OUT
high impedance
Delay time from PCM_CLK high to PCM_OUT
high impedance
Set-up time for PCM_IN valid to PCM_CLK low
Hold time for PCM_CLK low to PCM_IN invalid
Delay time from PCM_CLK high to PCM_OUT
t
dmclksyncl
Delay time from
PCM_CLK low to
PCM sync low (long
frame sync only)
Parameter
t
dmclksynch
Delay time from
PCM_CLK high to
PCM sync high
ns
Table 15: PCM Master Mode Timing Parameters