User's Manual

Bluegiga Technologies Oy
Page 34 of 52
Figure 25: PCM Slave Timing Short Frame Sync
14.2.5 PCM_CLK and PCM_SYNC Generation
BT111 has 2 methods of generating PCM_CLK and PCM_SYNC in master mode:
 Generating these signals by DDS from BT111 internal 4MHz clock. Using this mode limits PCM_CLK
to 128, 256 or 512kHz and PCM_SYNC to 8kHz.
 Generating these signals by DDS from an internal 48MHz clock, enables a greater range of
frequencies to be generated with low jitter but consumes more power. To select this second method
set bit 48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long
frame sync, the length of PCM_SYNC is either 8 or 16 cycles of PCM_CLK, determined by
LONG_LENGTH_SYNC_EN in PSKEY_PCM_CONFIG32.
Following equation describes PCM_CLK frequency when generated from the internal 48MHz clock:
Equation 1: PCM_CLK Frequency Generated Using the Internal 48MHz Clock
Set the frequency of PCM_SYNC relative to PCM_CLK using following equation:
Equation 2: PCM_SYNC Frequency Relative to PCM_CLK
CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an
example, to generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set
PSKEY_PCM_LOW_JITTER_CONFIG to 0x08080177.