Data Sheet

Table Of Contents
Alternate LOCATION
Functionality 0 - 3 4 - 7 Description
TIM3_CC2
0: PA15
2: PE5
3: PE7
4: PA2
5: PA5 Timer 3 Capture Compare input / output channel 2.
TIM4_CC0 2: PF5 Timer 4 Capture Compare input / output channel 0.
TIM5_CC0 1: PE7 Timer 5 Capture Compare input / output channel 0.
TIM5_CC1 0: PE5 6: PF10 Timer 5 Capture Compare input / output channel 1.
TIM5_CC2 0: PE6 6: PF11 Timer 5 Capture Compare input / output channel 2.
TIM6_CC0 5: PB13 Timer 6 Capture Compare input / output channel 0.
TIM6_CC1 5: PB14 Timer 6 Capture Compare input / output channel 1.
TIM6_CC2 7: PD6 Timer 6 Capture Compare input / output channel 2.
TIM6_CDTI1 2: PE5 Timer 6 Complimentary Dead Time Insertion channel 1.
TIM6_CDTI2 2: PE6 Timer 6 Complimentary Dead Time Insertion channel 2.
U0_CTS 2: PA5 UART0 Clear To Send hardware flow control input.
U0_RTS 2: PA6 5: PD6 UART0 Request To Send hardware flow control output.
U0_RX
2: PA4 4: PC5
5: PF2
UART0 Receive input.
U0_TX
2: PA3 4: PC4
5: PF1
UART0 Transmit output. Also used as receive input in half duplex communication.
U1_CTS 2: PB11 4: PC4 UART1 Clear To Send hardware flow control input.
U1_RTS
2: PB12
3: PE5
4: PC5
UART1 Request To Send hardware flow control output.
U1_RX 1: PF11 UART1 Receive input.
U1_TX 1: PF10 UART1 Transmit output. Also used as receive input in half duplex communication.
US0_CLK 1: PE5 4: PB13 USART0 clock input / output.
US0_CS 4: PB14 USART0 chip select input / output.
US0_CTS
0: PE14 4: PB6
5: PB11
USART0 Clear To Send hardware flow control input.
US0_RTS
0: PE15 4: PB5
5: PD6
USART0 Request To Send hardware flow control output.
US0_RX
1: PE6 USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
US0_TX
1: PE7 USART0 Asynchronous Transmit. Also used as receive input in half duplex communica-
tion.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
US1_CLK
2: PF0 5: PB11
6: PE5
USART1 clock input / output.
WGM160P Wi-Fi
®
Module Data Sheet
Pin Descriptions
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