WT21 DATA SHEET Wednesday, 11 November 2009 Version 1.
Copyright © 2000-2009 Bluegiga Technologies All rights reserved. Bluegiga Technologies assumes no responsibility for any errors which may appear in this manual. Furthermore, Bluegiga Technologies reserves the right to alter the hardware, software, and/or specifications detailed here at any time without notice and does not make any commitment to update the information contained here. Bluegiga’s products are not authorized for use as critical components in life support devices or systems.
VERSION HISTORY Version Comment 0.1 First draft 0.2 Block diagram, descriptions added 0.3 Preliminary version 0.4 Fixed ordering codes added captions 0.5 Power control and regulation info added. Layout guide updated. Minor updates and fixes. 1.0 Electrical characteristic added. Some minor updates. 1.1 Function of the regulator enable pin corrected. Some minor updates. 1.2 New template 1.3 Pinout fixed (GND pins 1 – 3 removed, pin 23 grounded). Layout guide updated. 1.
TABLE OF CONTENTS 1 Ordering Information ................................................................................................8 2 Pinout and Terminal Description .................................................................................9 3 Microcontroller, Memory and Baseband Logic.............................................................. 12 3.1 4 3.1.1 AuriStream CODEC Requirements .................................................................. 13 3.1.
8.1.2 Long Frame Sync......................................................................................... 27 8.1.3 Short Frame Sync........................................................................................ 28 8.1.4 Multi-Slot Operation..................................................................................... 28 8.1.5 GCI Interface .............................................................................................. 29 8.1.6 Slots and Sample Formats ...........
14.5 15 Qualified Antenna Types for WT21-N .............................................................. 53 Contact Information .............................................................................................
WT21 Bluetooth® HCI Module DESCRIPTION WT21 is intended for Bluetooth applications where a host processor is capable of running the Bluetooth software stack. WT21 only implements the low level Bluetooth Host Controller Interface (HCI) but still offers advantages of a module - easy implementation and certifications. APPLICATIONS: • • • PCs and laptops PDAs Embedded systems FEATURES: • • • • • • • • • • • Fully Qualified Bluetooth v2.
1 Ordering Information WT21-A-HCI Fimrware HCI = HCI firmware HW version A = Chip antenna, extended temperature range N = RF pin, extended temperature range Product series Bluegiga Technologies Oy Page 8 of 54
2 Pinout and Terminal Description RFTP GND GND GND GND GND GND GND GND RST# SPI_MOSI GND PCM_SYNC GND VDD_PADS 1V8_OUT SDIO_CMD VREGIN SDIO_SD_CS# VREG_ENA 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 GND 29 28 UART_RX UART_CTS# 27 UART_TX 26 32kHz 25 GND 24 PIO7 PIO9 23 15 UART_RTS# SDIO_CLK PIO1 GND 14 PCM_CLK 22 13 GND PIO5 12 PCM_OUT PIO4 11 PCM_IN GND 20 21 10 GND PIO3 9 SPI_MISO 19 8 GND 18 7 SPI_CLK GND 6 GND PIO2 5 SPI_CS# 1
POWER SUPPLIES PIN NUMBER DESCRIPTION VREGIN 12 Input for the internal 1,8V regulator 1v8_OUT 11 1,8V regulator output VREG_ENA 13 Take high to enable internal voltage regulators 4-10, 15-16, 28, 43-50 GND VDD_PADS 33 Ground Positive supply for the digital interfaces Table 2: Terminal Descriptions PIO PORT PIN PAD TYPE NUMBER DESCRIPTION PIO[1] 14 Bi-directional, programmamble strength internal pull-down/pull-up Programmamble input/output line PIO[2] 17 Bi-directional, programmambl
SPI INTERFACE PIN NUMBER PAD TYPE DESCRIPTION Output, tri-state, weak internal pull-down Synchronous data output PCM_OUT 36 PCM_IN 37 PCM_SYNC 34 Bi-directional, weak internal pull-down Synchronous data sync PCM_CLK 35 Bi-directional, weak internal pull-down Synchronous data clock Input, weak internal pullSynchronous data input down Table 4: Terminal Descriptions PIN SDIO/CSPI/UA NUMBER RT Interfaces SDIO_DATA[0] 25 CSPI_MISO UART_TX SDIO_DATA[1] 26 CSPI_INT UART_RTS# SDIO_DATA[2] 27 UART
3 Microcontroller, Memory and Baseband Logic 3.1 AuriStream CODEC The AuriStream CODEC works on the principle of transmitting the delta between the actual value of the signal and a prediction rather than the signal itself. Hence, the information transmitted is reduced along with the power requirement. The quality of the output depends on the number of bits used to represent the sample.
3.1.1 AuriStream CODEC Requirements AuriStream supports the following modes of operation: Table 7: AuriStream Supported Bitrates Table Key: = Standard Mode = Optional Mode Where possible, AuriStream shares hardware between the encoder and decoder as well as the G726 and G722 implementations of the standard. The 40kbs and 20kbs modes of the G722 codec are specific to CSR. The AuriStream module will be required to support the 3Mbps stream transmitted by the BT radio.
Figure 3: AuriStream CODEC and the CVSD CODEC The AuriStream CODEC is controlled by the TX_RX_VOICEmain block and the processor. Raw data from the host is read from the MMU by the transmit block. This data is fed via the TX_RX_VOICE_MAIN module to the required CODEC, the encoded data is then fed back to the transmit block for broadcast over the Bluetooth interface. During reception, the data is sourced from the radio and applied to the required CODEC.
The following voice data translations and operations are performed by firmware: • • • • A-law/µ-law/linear voice data (from host) A-law/µ-law/Continuously variable Slope Delta (CVSD) (over the air) Voice interpolation for lost packets Rate mismatches The hardware supports all optional and mandatory features of Bluetooth v2.1 + EDR including AFH and eSCO. 3.5 WLAN Coexistence Dedicated hardware is provided to implement a variety of coexistence schemes.
4 Clock Generation WT21 uses an internal 26 MHz crystal as a Bluetooth reference clock. All WT21 internal digital clocks are generated using a phase locked loop, which is locked to the 26 MHz reference clock. Also supplied to the digits is a watchdog clock, for use in low power modes. This uses a frequency of 32.768kHz from CLK_32K, or an internally generated reference clock frequency of 1kHz, determined by PSKEY_DEEP_SLEEP_EXTERNAL_CLOCK_SOURCE.
5 Serial Peripheral Interface (SPI) 5.1 WT21 Serial Peripheral Interface (SPI) SPI is used for debuging primarily. This section details the considerations required when interfacing to WT21 via the SPI. Data may be written or read one word at a time or the auto increment feature may be used to access blocks. 5.2 Instruction Cycle WT21 is the slave and receives commands on SPI_MOSI and outputs data on SPI_MISO. Table 8 shows the instruction cycle for an SPI transaction.
Figure 5: SPI Write Operation 5.2.2 Reading from the Device Reading from WT21 is similar to writing to it. An 8-bit read command (00000011) is sent first (C [7:0]), followed by the address of the location to be read (A[15:0]). WT21 then outputs on SPI_MISO a check word during T[15:0] followed by the 16-bit contents of the addressed location during bits D[15:0]. The check word is composed of {command, address [15:8]}. The check word may be used to confirm a read operation to a memory location.
6 Host Interfaces 6.1 Host Selection The MCU selects the UART/SDIO interfaces by reading PIO[4] at boot-time. When PIO[4] is high, the SDIO interface is enabled; when PIO[4] is low, the UART is enabled. If in UART mode, the MCU selects the UART transfer protocol automatically using the unused SDIO pins shown in Table 9 SDIO_CLK 0 0 1 1 SDIO_CMD 0 1 0 1 Protocol bcsp h4 h4ds h5 Table 9: SDIO_CLK and SDIO_CMD transfer Protocols 6.
UART configuration parameters, such as baud rate and packet format, are set using WT21 firmware. Note: An accelerated serial port adapter is required to communicate with the UART at maximum baud rate using a standard PC. Table 10: Possible UART Settings Note: Baud rate is the measure of symbol rate i.e. , the number of distinct symbol changes (signaling events) made to transmission medium per second in a digitally modulated signal.
Table 11: Standard Baud Rates 6.2.1 UART Configuration While Reset is Active The UART interface for WT21 is tri-state while the chip is being held in reset. This allows the user to daisy chain devices onto the physical UART bus. The constraint on this method is that any devices connected to this bus must tri-state when WT21 reset is de-asserted and the firmware begins to run.
7 CSR Serial Peripheral Interface (CSPI) The CSPI is a host interface which shares pins with the SDIO. It has been defined by CSR with the intention of producing a very simple interface. This has two advantages: • It allows maximum compatibility with the possible host drivers • It minimizes the host software effort needed to form that data to be sent (e.g.
7.1.2 CSPI Register Write Cycle The command and address are locked into the slave, followed by 16bits of write data. An Error Byte is returned on the MISO signal indicating whether or not the transfer has been successful. Figure 9: CSPI Register Write Cycle 7.1.3 CSPI Register Read Cycle The command and address field are clocked into the slave, the slave then returns the following: • • • Bytes of badding data (MISO held low) Error byte 16-bits of read data Figure 10: CSPI Register Read Cycle 7.1.
7.1.5 CSPI Register Read Cycle Burst reads have a programmable amount of padding data that is returned by the slave. 0-15 bytes are returned as defined in the BurstPadding register. Following this the Error byte is returned followed by the data. Once the transfer has started, no further padding is needed. A FIFO within SDIO_TOP will pre-fetch the data. The address is not retransmitted, and is autoupdated within the slave.
7.2 SDIO Interface This is a host interface which allows a Secure Digital Input Output(SDIO) host to gain access to the internals of the chip. It provides all defined slave modes (SPI, SD 1bit, SD 4bit), but not SD host function. The function provided includes generating responses to each command in hardware and implementing the state machines defined in the SDIO specification.
8 Audio Interfaces 8.1 PCM Interface The audio Pulse Code Modulation(PCM) interface supports continuous transmission and reception of PCM encoded audio data over Bluetooth. Pulse Code Modulation (PCM) is a standard method used to digitise audio (particularly voice) for transmission over digital communication channels. Through its PCM interface, WT21 has hardware support for continual transmission and reception of PCM data, thus reducing processor overhead for wireless headset applications.
Figure 13: WT21 as a PCM Interface Master Figure 14: WT21 as a PCM Interface Slave 8.1.2 Long Frame Sync Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples. In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When WT21 is configured as PCM master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8-bits long.
Figure 15: Long Frame Sync (Shown with 8-bit Companded Sample) BlueCore6-ROM (QFN) samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge. 8.1.3 Short Frame Sync In Short Frame Sync, the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always one clock cycle long.
Figure 17: Multi-Slot Operation with Two Slots and 8-bit Companded Samples 8.1.5 GCI Interface WT21 is compatible with the General Circuit Interface (GCI), a standard synchronous 2B+D ISDN timing interface. The two 64kbps B channels can be accessed when this mode is configured. Figure 18: GCI Interface The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz. With WT21 in Slave mode, the frequency of PCM_CLK can be up to 4.096MHz. 8.1.
Figure 19: 16-Bit Slot Length and Sample Formats 8.1.7 Additional Features WT21 has a mute facility that forces PCM_OUT to be 0. In master mode, PCM_SYNC may also be forced to 0 while keeping PCM_CLK running which some CODECS use to control power down.
8.1.8 PCM Timing Information Figure 20: PCM Master Timing a) Assumes normal system clock operation. Figures will vary during low power modes, when system clock speeds are reduced.
Figure 21: PCM Master Timing Long Frame Sync Figure 22: PCM Master Timing Short Frame Sync Bluegiga Technologies Oy Page 32 of 54
Table 13: PCM Slave Timing Figure 23: PCM Slave Timing Long Frame Sync Bluegiga Technologies Oy Page 33 of 54
Figure 24: PCM Slave Timing Short Frame Sync 8.1.9 PCM_CLK and PCM_SYNC Generation WT21 has two methods of generating PCM_CLK and PCM_SYNC in master mode. The first is generating these signals by Direct Digital Synthesis(DDS) from WT21 internal 4MHz clock. Using this mode limits PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to 8kHz.
Table 14: PSKEY_PCM_LOW_JITTER_CONFIG Description Bluegiga Technologies Oy Page 35 of 54
Table 15: PSKEY_PCM_CONFIG32 Description Bluegiga Technologies Oy Page 36 of 54
Table 16: PSKEY_PCM_SYNC_MULT Description 8.2 Digital Audio Interface (I2S) The digital audio interface supports the industry standard formats for I2S, left-justified (LJ) or right-justified(RJ). The interface shares the same pins as the PCM interface, which means each audio bus is mutually exclusive in its usage. Table 17 lists these alternative functions. Figure 26 shows the timing diagram. Table 17: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface.
Figure 25: Digital Audio Interface Modes The internal representation of audio samples within BlueCore6-ROM (QFN) is 16-bit and data on SD_OUT is limited to 16-bit per channel.
Figure 26: Digital Audio Interface Slave Timing Table 20: Digital Audio Interface Master Timing Figure 27: Digital Audio Interface Master Timing Bluegiga Technologies Oy Page 39 of 54
9 Power Control and Regulation 9.1 Power Control and Regulation WT21 contains two linear regulators. • • A high voltage regulator to generate 1,8 V rail for the module I/Os A low voltage regulator to supply the 1,5 V core from the 1,8 V rail The module can be powered from a high-voltage rail through both regulators and the output of the high-voltage regulator can be used as a supply voltage for the digital interfaces of the module (VDD_PADS).
9.4 Digital Pin States on Reset The digital I/O interfaces on the WT21 device are optimised for minimum power consumption after initialisation of digital interfaces. Table 21 shows the pin states of WT21 on reset. Pull-up (PU) and pull-down (PD) default to weak values unless specified otherwise.
Pin Name / Group Reset / Control RST# Pin Name / Group No Core Voltage Reset Pull R I/O I/O Type Digital Input PU PCM Interface PCM_IN PCM_OUT PCM_CLK PCM_SYNC Pin Name / Group SPI Interface SPI_MOSI SPI_CLK SPI_CS# SPI_MISO Pin Name / Group PIOs PIO[0] PIO[1] PIO[2] PIO[3] PIO[4] PIO[5] PIO[7] PIO[9] Pin Name / Group Clock CLK_32K PU No Core Voltage Reset Pull R I/O I/O Type Digital Interfaces - SDIO SDIO_DATA[3] Digital bi-directional SDIO_DATA[2] Digital bi-directional SDIO_DATA[1] Digital bi-di
10 Bluetooth Radio 10.1 Bluetooth Receiver The receiver features a near-zero Intermediate Frequency (IF) architecture that allows the channel filters to be integrated onto the die. Sufficient out-of-band blocking specification at the Low Noise Amplifier (LNA) input allows the receiver to be used in close proximity to Global System for Mobile Communications(GSM) and Wideband Code Division Multiple Access (WCDMA) cellular phone transmitters without being desensitised.
11 Electrical Characteristics 11.1 Absolute Maximum Ratings Rating Storage Temperature IO Voltage VDD_PADS Min -40 -0.4 Max 85 3.7 Unit °C V Supply Voltage VREG_IN, VREG_ENA -0.4 4.9 V VSS-0.4 VDD+0.4 V Other Terminal Voltages Table 22: Absolute Maximum Ratings 11.2 Recommended Operating Conditions Rating Operating Temperature Range IO Voltage VDD_PADS Min TBD 1.7 Max TBD 3.7 Unit °C V Table 23: Recommended Operating Conditions 11.3 Input/Output Terminal Characteristics 11.3.
11.3.2 Digital Digital Terminals Input Voltage Levels VIL input logic level low 1.7V ≤ VDD ≤ 3.6V VIH input logic level high 1.7V ≤ VDD ≤ 3.6V Output voltage levels VOL output logic level low 1.7V ≤ VDD ≤ 3.6V, (Io = 4.0 mA) VOH output logic level high 1.7V ≤ VDD ≤ 3.6V, (Io = -4.0 mA) Input Tri-state Current with: Strong pull-up Strong pull-down Weak pull-up Weak pull-down I/O pad leakage curren Cl input capacitance Min Typ Max Unit -0.4 - 0.25xVDD V 0.7VDD - VDD+0.3 V - - 0.125 V VDD-0.
11.4 Power Consumption Operation Mode Page scan, time interval 1.28s Inquiry and page scan, time interval1,28s ACL no trafic ACL with file transfer ACL 40ms sniff ACL 1,28s sniff eSCO EV5 eSCO EV3 eSCO EV3 - hands-free - setting S1 SCO HV1 SCO HV3 SCO HV3 30ms sniff ACL no traffic ACL with file transfer ACL 40ms sniff ACL 1.
12 Physical Dimensions Figure 29: Physical dimensions Figure 30: WT21-A recommended PCB land pattern Bluegiga Technologies Oy Page 47 of 54
Figure 31: WT21-N recommended PCB land pattern Bluegiga Technologies Oy Page 48 of 54
Figure 32: Detailed dimensions Bluegiga Technologies Oy Page 49 of 54
13 13.1 Layout Guidelines WT21-N RF output can be taken directly from the RF test point (RFTP) of the module. RFTP has a signal pin surrounded by a ground. Dimensions for the RFTP are shown in the figure below. Use 50 ohm trace to route RF from RFTP. With WT21-A leave RFTP floating and do not place copper directly under RFTP. Figure 33: Dimensions of the RFTP 13.
Do not connect RFTP for WT21-A. See figure 32 for the recommended PCB land patern. The impedance matching of the antenna is design for the evaluation board of WT21. For an optimal performance of the antenna the layout should strictly follow the layout example shown in figure 31 and the thickness of FR4 should be 1,6 mm. Any dielectric material close to the antenna will change the resonant frequency and it is recommended not to place a plastic case or any other dielectric closer than 5 mm from the antenna.
14 Certifications WT21 is compliant to the following specifications. 14.1 Bluetooth WT21 module is Bluetooth qualified and listed as a controller subsystem and it is Bluetooth compliant to the following profiles of the core spec version 2.1/2.1+EDR. RF, Baseband, Link Manager, Host Controller Interface, Serial Port Profile and RFCOMM with TS 07.10. Bluetooth QDID: 14.2 B016019 FCC This device complies with Part 15 of the FCC Rules.
14.3 CE WT21 meets the requirements of the standards below and hence fulfills the requirements of EMC Directive 89/336/EEC as amended by Directives 92/31/EEC and 93/68/EEC within CE marking requirement. • • 14.4 Electromagnetic emission EN 301 489-17 V.1.2.
15 Contact Information Sales: sales@bluegiga.com Technical support: support@bluegiga.com http://www.bluegiga.com/techforum/ Orders: orders@bluegiga.com Head Office / Finland: Phone: +358-9-4355 060 Fax: +358-9-4355 0660 Street Address: Sinikalliontie 5A 02630 ESPOO FINLAND Postal address: P.O. BOX 120 02631 ESPOO FINLAND Sales Office / USA: Phone: (781) 556-1039 Bluegiga Technologies, Inc.
