WT41u DATA SHEET Monday, 21 November 2016 Version 0.8.
VERSION HISTORY Version Comment 0.8 First version 0.8.1 Table reformatting, value updates etc 0.8.2 Replaced “Bluecore4” with “chipset”, added ordering codes 0.8.
TABLE OF CONTENTS 1 Ordering Information......................................................................................................................................6 2 Pinout and Terminal Description ...................................................................................................................7 3 Electrical Characteristics ............................................................................................................................ 11 3.
9.8 PCM_CLK and PCM_SYNC Generation ............................................................................................ 32 9.9 PCM Configuration .............................................................................................................................. 33 10 I/O Parallel Ports ..................................................................................................................................... 36 10.1 11 PIO Defaults .........................................
WT41u Bluetooth® Module DESCRIPTION WT41u is a long range class 1, Bluetooth® 2.1 + EDR module. WT41u is a highly integrated and sophisticated Bluetooth® module, containing all the necessary elements from Bluetooth® radio and a fully implemented protocol stack. Therefore WT41u provides an ideal solution for developers who want to integrate Bluetooth® wireless technology into their design with limited knowledge of Bluetooth® and RF technologies.
1 Ordering Information Firmware U.FL Connector Internal chip antenna iWRAP 5.6 firmware, reel WT41u-E-AI56 WT41u-A-AI56 iWRAP 5.5 firmware, reel WT41u-E-AI55 WT41u-A-AI55 HCI firmware, BT2.1 + EDR, reel WT41u-E-HCI21001 WT41u-A-HCI21001 iWRAP 5.6 firmware with iAP, reel WT41u-E-AI56IAP WT41u-A-AI56IAP iWRAP 5.6 firmware, cut reel WT41u-E-AI56C WT41u-A-AI56C iWRAP 5.5 firmware, cut reel WT41u-E-AI55C WT41u-A-AI55C HCI firmware, BT2.
GND GND GND GND GND GND GND 59 58 57 56 55 54 53 2 Pinout and Terminal Description 51 RF RFGND 50 GND GND GND GND GND GND AIO UART_TX PIO5 SPI_MOSI SPI_MISO SPI_CLK SPI_CSB GND PIO7 PIO6 RESET VDD GND 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 GND PCM_OUT GND GND GND PIO4 GND GND GND GND GND GND GND GND GND GND VDD_PA PIO2 PIO3 UART_RTS UART_RX GND USB+ USBUART_CTS PCM_IN PCM_CLK PCM_SYNC GND 24 25 26 27 28 29 30 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Pins 1 and 52
Pad name Pad number Pad type Description NC 1, 52 Not connected RESET 33 Digital input GND 2-10, 16, 23, 24, 26-28, 30, 31, 36, 44-49, 5359 Ground RF 51 Not connected RFGND 50 Ground VDD_PA 11 Supply voltage Supply voltage for the RF power amplifier and low noise amplifier VDD 32 Supply voltage Supply voltage for the Bluetooth chipset Pins 1 and 52 are not present on the footprint Active low reset with weak internal pull-up.
PCM signal Pad number Pad type Description PCM_OUT 25 Output, weak internal pull-down PCM_IN 20 Input, weak internal pull-down Synchronous data input PCM_SYNC 22 Bi-directional, weak internal pull-down Synchronous data sync PCM_CLK 21 Bi-directional, weak internal pull-down Synchronous data clock Synchronous data output Table 4: PCM Terminal Descriptions UART signal Pad number Pad type Description UART_TX 42 Output, pull-up weak internal UART data output, active high UART_RTS#
SPI signal Pad number Pad type SPI_MOSI 40 Input, weak internal pull-down SPI_CS# 37 Input, weak internal pull-up SPI_CLK 38 Input, weak internal pull-down SPI_MISO 39 Output, weak internal pull-down Description SPI data input Chip select, active low SPI clock SPI data output Table 7: Terminal Descriptions Silicon Laboratories Finland Oy Page 10 of 45
3 Electrical Characteristics 3.1 Absolute Maximum Ratings Specification Min Max Unit Storage temperature -40 85 °C VDD_PA, VDD -0.4 3.7 V VSS-0.4 VDD+0.4 V Specification Min Max Unit Operating temperature -40 85 °C VDD_PA*, VDD 3.0 3.6 V Other terminal voltages Table 8: Absolute Maximum Ratings 3.2 Recommended Operating Conditions *) VDD_PA has an effect on the RF output power.
3.3 Input / Output Terminal Characteristics 3.3.1 Input/Output Terminal Characteristics (Digital) Digital Terminals Min Typ Max Unit 2.7 V ≤ VDD ≤ 3.0 V -0.4 - 0.8 V 1.7 V ≤ VDD ≤ 1.9 V -0.4 - 0.4 V 0.7 VDD - VDD + 0.4 V - - 0.2 V - - 0.4 V VOL output logic level high (IO = 4.0 mA) 2.7V ≤ VDD ≤ 3.0 VDD - 0.2 - V VOL output logic level high (IO = 4.0 mA) 1.7V ≤ VDD ≤ 1.9 VDD - 0.4 - V -100 -40 -10 µA 10 40 100 µA Weak pull-up -5.0 -1.0 -0.
3.3.2 Input/Output Terminal Characteristics (USB) USB Terminals Min VDD_USB for correct USB operation 3.1 Typ Max Unit 3.6 V Input Threshold VIL input logic level log VIH input logic level high - - 0.3VDD_USB V 0.7VDD_USB - - V 3.
3.5 Transmitter Performance For BDR RF characteristic Min Typ Max Bluetooth specification Unit Max transmit power 17 18.4 20 <20 dBm Transmit power variation over temperature range +/-0.
3.6 Receiver Performance Antenna gain not taken into account Characteristic, VDD=3.3V, room temperature Packet type Typ Bluetooth specification Unit DH1 TBD -70 dBm DH5 -92 dBm 2-DH1 -97 dBm 2-DH5 TBD dBm 3-DH1 TBD dBm 3-DH5 TBD dBm TBD dBm Sensitivity for 0.1% BER Sensitivity variation over temperature range Table 11: Receiver sensitivity 3.
4 Physical Dimensions Figure 4: Physical dimensions (top view) Figure 5: Dimensions for the RF pin used as antenna connection on WT41u-N (top view) Silicon Laboratories Finland Oy Page 16 of 45
Figure 6: Dimensions of WT41u-E Figure 7: Dimensions of WT41u-A Silicon Laboratories Finland Oy Page 17 of 45
Figure 8: Recommended land pattern Silicon Laboratories Finland Oy Page 18 of 45
• – Do not route supply voltage traces across separated GND regions so th path for the return current is cut MIC input – Place LC filtering and DC coupling capacitors symmetrically as close to pins as possible –5 Place biasing resistors symmetrically as close to microhone as pos LayoutMIC Guidelines –Use Make sure that the bias trace does not cross separated GND regions (D good layout practices to avoid excessive noise coupling to supply voltage traces or sensitive analog signal traces, such analog the aud
6 UART Interface This is a standard UART interface for communicating with other serial devices.WT41u UART interface provides a simple mechanism for communicating with other serial devices using the RS232 protocol. Four signals are used to implement the UART function. When WT41u is connected to another digital device, UART_RX and UART_TX transfer data between the two devices.
Equation 1: Data Rate Data rate [bits/s] Persistent store value (Hex) Error [bits/s] Error [%] 1200 0x0005 5 1.73 2400 0x000A 10 1.73 4800 0x0014 20 1.73 9600 0x0027 39 -0.82 19200 0x004F 79 0.45 38400 0x009D 157 -0.18 57600 0x00EC 236 0.03 76800 0x013B 315 0.14 115200 0x01D8 472 0.03 230400 0x03B0 944 0.03 460800 0x075F 1887 -0.02 921600 0x0EBF 3775 0 1382400 0x161E 5662 -0.
6.1 UART Bypass Figure 12: UART Bypass Architecture 6.2 UART Configuration While Reset is Active The UART interface for WT41u while the chip is being held in reset is tristate. This will allow the user to daisy chain devices onto the physical UART bus. The constraint on this method is that any devices connected to this bus must tristate when WT41u reset is de-asserted and the firmware begins to run. 6.
7 USB Interface This is a full speed (12Mbits/s) USB interface for communicating with other compatible digital devices. WT41u acts as a USB peripheral, responding to requests from a master host controller such as a PC. The USB interface is capable of driving a USB cable directly. No external USB transceiver is required. The device operates as a USB peripheral, responding to requests from a master host controller such as a PC. Both the OHCI and the UHCI standards are supported.
Figure 13: USB Connections for Self-Powered Mode The terminal marked USB_ON can be any free PIO pin. The PIO pin selected must be registered by setting PSKEY_USB_PIO_VBUS to the corresponding pin number. Identifier Value Function Rs 27Ω nominal Impedance matching to USB cable Rvb1 22kΩ 5% VBUS ON sense divider Rvb2 47kΩ 5% VBUS ON sense divider Figure 14: USB Interface Component Values 7.
Figure 15: USB Connections for Bus-Powered Mode 7.6 USB Suspend Current All USB devices must permit the USB controller to place them in a USB suspend mode. While in USB Suspend, bus-powered devices must not draw more than 2.5mA from USB VBUS (self-powered devices may draw more than 2.5mA from their own supply). This current draw requirement prevents operation of the radio by bus-powered devices during USB Suspend.
Figure 16: USB_Detach and USB_Wake_Up Signals 7.8 USB Driver A USB Bluetooth device driver is required to provide a software interface between the chipset and Bluetooth software running on the host computer. Please, contact Silicon Labs support at http://www.silabs.com for suitable drivers. 7.9 USB v2.0 Compliance and Compatibility Although WT41u meets the USB specification, Silicon Labs cannot guarantee that an application circuit designed around the module is USB compliant.
8 Serial Peripheral Interface (SPI) The SPI port can be used for system debugging. It can also be used for programming the Flash memory and setting the PSKEY configurations. WT41u uses 16-bit data and 16-bit address serial peripheral interface, where transactions may occur when the internal processor is running or is stopped. SPI interface is connected using the MOSI, MISO, CSB and CLK pins. Please, contact the Silicon Labs support at http://www.silabs.
9 PCM Codec Interface PCM is a standard method used to digitize audio (particularly voice) for transmission over digital communication channels. Through its PCM interface, WT41u has hardware support for continual transmission and reception of PCM data, thus reducing processor overhead for wireless headset applications. WT41u offers a bidirectional digital audio interface that routes directly into the baseband layer of the on-chip firmware. It does not pass through the HCI protocol layer.
Figure 18: PCM Interface Slave 9.2 Long Frame Sync Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples. In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When WT41u is configured as PCM master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8-bits long. When WT41u is configured as PCM Slave, PCM_SYNC may be from two consecutive falling edges of PCM_CLK to half the PCM_SYNC rate, i.e., 62.5s long.
Figure 20: Short Frame Sync (Shown with 16-bit Sample) As with Long Frame Sync, WT41u samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge. 9.4 Multi-slot Operation More than one SCO connection over the PCM interface is supported using multiple slots. Up to three SCO connections can be carried over any of the first four slots.
Figure 22: GCI Interface The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz. With WT41u in Slave mode, the frequency of PCM_CLK can be up to 4.096MHz. 9.6 Slots and Sample Formats WT41u can receive and transmit on any selection of the first four slots following each sync pulse. Slot durations can be either 8 or 16 clock cycles. Durations of 8 clock cycles may only be used with 8-bit sample formats. Durations of 16 clocks may be used with 8-bit, 13-bit or 16-bit sample formats.
Figure 23: 16-bit Slot Length and Sample Formats 9.7 Additional Features WT41u has a mute facility that forces PCM_OUT to be 0. In master mode, PCM_SYNC may also be forced to 0 while keeping PCM_CLK running which some codecs use to control power down. 9.8 PCM_CLK and PCM_SYNC Generation WT41u has two methods of generating PCM_CLK and PCM_SYNC in master mode. The first is generating these signals by DDS from the chipset internal 4MHz clock.
Equation 2: PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock The frequency of PCM_SYNC relative to PCM_CLK can be set using Equation 3: Equation 3: PCM_SYNC Frequency Relative to PCM_CLK CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an example, to generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set PSKEY_PCM_LOW_JITTER_CONFIG to 0x08080177. 9.
Name Bit position Description - 0 Set to 0 SLAVE MODE EN 1 0 selects Master mode with internal generation of PCM_CLK and PCM_SYNC. 1 selects Slave mode requiring externally generated PCM_CLK and PCM_SYNC. This should be set to 1 if 48M_PCM_CLK_GEN_EN (bit 11) is set.
Name Bit position Description CNT LIMIT [12:0] Sets PCM_CLK counter limit CNT RATE [23:16] Sets PCM_CLK count rate SYNC LIMIT [31:24] Sets PCM_SYNC division relative to PCM_CLK Table 16: PSKEY_PCM_LOW_JITTER_CONFIG Description Silicon Laboratories Finland Oy Page 35 of 45
10 I/O Parallel Ports Six lines of programmable bidirectional input/outputs (I/O) are provided. All the PIO lines are power from VDD. PIO lines can be configured through software to have either weak or strong pull-ups or pull-downs. All PIO lines are configured as inputs with weak pull-downs at reset. Any of the PIO lines can be configured as interrupt request lines or as wake-up lines from sleep modes. WT41u has a general purpose analogue interface pin AIO[1].
11 Reset WT41u may be reset from several sources: RESET pin, power on reset, a UART break character or via software configured watchdog timer. The RESET pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. A reset will be performed between 1.5 and 4.0ms following RESETB being active. It is recommended that RESET be applied for a period greater than 5ms. The power on reset occurs when the VDD_CORE supply internally to the module falls below typically 1.
11.
12 Certifications 12.1 Bluetooth The WT41u module is Bluetooth qualified and listed as a controller subsystem and it is Bluetooth compliant to the following profiles of the core spec version 2.1/2.1+EDR. Baseband HCI Link Manager Radio The WT41u-E and WT41u-N radios have been tested using an external antenna with a maximum gain of 2.3 dBi and the Bluetooth qualification is valid for any antenna with the same or less gain. 12.2 FCC This device complies with Part 15 of the FCC Rules.
The transmitter module must not be co-located or operating in conjunction with any other antenna or transmitter except in accordance with FCC multi-transmitter product procedures. As long as the two conditions above are met, further transmitter testing will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed (for example, digital device emissions, PC peripheral requirements, etc.).
The transmitter module must not be co-located or operating in conjunction with any other antenna or transmitter. As long as the two conditions above are met, further transmitter testing will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed (for example, digital device emissions, PC peripheral requirements, etc.).
Le module émetteur ne doit pas être installé au même endroit ou fonctionner conjointement avec toute autre antenne ou émetteur. Dès lors que les deux conditions ci-dessus sont respectées, d'autres tests de l'émetteur ne sont pas obligatoires.
“This equipment contains specified radio equipment that has been certified to the Technical Regulation Conformity Certification under the Radio Law.
12.6 Qualified Antenna Types for WT41u-E and WT41u-N This device has been designed to operate with a standard 2.14 dBi dipole antenna. Any antenna of a different type or with a gain higher than 2.14 dBi is strictly prohibited for use with this device. Using an antenna of a different type or gain more than 2.14 dBi will require additional testing for FCC, CE and IC. The required antenna impedance is 50 Ω. Antenna type Maximum gain Dipole 2.
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