C8051F340/1/2/3/4/5/6/7 Full Speed USB Flash MCU Family Analog Peripherals - 10-Bit ADC • • Instructions in 1 or 2 system clocks - Two comparators - Internal voltage reference - Brown-out detector and POR Circuitry USB Function Controller - USB specification 2.0 compliant - Full speed (12 Mbps) or low speed (1.
C8051F340/1/2/3/4/5/6/7 NOTES: 2 Rev. 0.
C8051F340/1/2/3/4/5/6/7 Table Of Contents 1. System Overview.................................................................................................... 17 1.1. CIP-51™ Microcontroller Core.......................................................................... 21 1.1.1. Fully 8051 Compatible.............................................................................. 21 1.1.2. Improved Throughput ............................................................................... 21 1.1.3.
C8051F340/1/2/3/4/5/6/7 9.3. Interrupt Handler ............................................................................................... 87 9.3.1. MCU Interrupt Sources and Vectors ........................................................ 87 9.3.2. External Interrupts .................................................................................... 87 9.3.3. Interrupt Priorities ..................................................................................... 88 9.3.4. Interrupt Latency ........
C8051F340/1/2/3/4/5/6/7 14. Oscillators ............................................................................................................. 135 14.1.Programmable Internal High-Frequency (H-F) Oscillator ............................... 136 14.1.1.Internal H-F Oscillator Suspend Mode ................................................... 136 14.2.Programmable Internal Low-Frequency (L-F) Oscillator ................................ 137 14.2.1.Calibrating the Internal L-F Oscillator......................
C8051F340/1/2/3/4/5/6/7 17.3.SMBus Operation ........................................................................................... 194 17.3.1.Arbitration............................................................................................... 195 17.3.2.Clock Low Extension.............................................................................. 196 17.3.3.SCL Low Timeout................................................................................... 196 17.3.4.
C8051F340/1/2/3/4/5/6/7 21.2.Timer 2 .......................................................................................................... 251 21.2.1.16-bit Timer with Auto-Reload................................................................ 251 21.2.2.8-bit Timers with Auto-Reload................................................................ 252 21.2.3.Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge ...... 253 21.3.Timer 3 .............................................................
C8051F340/1/2/3/4/5/6/7 NOTES: 8 Rev. 0.
C8051F340/1/2/3/4/5/6/7 List of Figures and Tables 1. System Overview Table 1.1. Product Selection Guide ........................................................................ 18 Figure 1.1. C8051F340/1/4/5 Block Diagram ........................................................... 19 Figure 1.2. C8051F342/3/6/7 Block Diagram ........................................................... 20 Figure 1.3. On-Chip Clock and Reset ...................................................................... 22 Figure 1.4.
C8051F340/1/2/3/4/5/6/7 8. Voltage Regulator (REG0) Table 8.1. Voltage Regulator Electrical Specifications............................................ 69 Figure 8.1. REG0 Configuration: USB Bus-Powered ............................................... 70 Figure 8.2. REG0 Configuration: USB Self-Powered ............................................... 70 Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled .............. 71 Figure 8.4. REG0 Configuration: No USB Connection.......................
C8051F340/1/2/3/4/5/6/7 Figure 16.2. USB0 Register Access Scheme......................................................... 166 Table 16.2. USB0 Controller Registers .................................................................. 169 Figure 16.3. USB FIFO Allocation .......................................................................... 171 Table 16.3. FIFO Configurations ............................................................................ 172 Table 16.4.
C8051F340/1/2/3/4/5/6/7 Figure 20.10. SPI Slave Timing (CKPHA = 0)........................................................ 240 Figure 20.11. SPI Slave Timing (CKPHA = 1)........................................................ 240 Table 20.1. SPI Slave Timing Parameters ............................................................. 241 21. Timers Figure 21.1. T0 Mode 0 Block Diagram.................................................................. 244 Figure 21.2. T0 Mode 2 Block Diagram......................
C8051F340/1/2/3/4/5/6/7 List of Registers SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 48 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . . . . . . . . . . . . . . . . . . 49 SFR Definition 5.3. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SFR Definition 5.4. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SFR Definition 5.5. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . .
C8051F340/1/2/3/4/5/6/7 SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control . . . . . . . . . . . . . . . . . . 138 SFR Definition 14.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 141 SFR Definition 14.5. CLKMUL: Clock Multiplier Control . . . . . . . . . . . . . . . . . . . . . . . 142 SFR Definition 14.6. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 SFR Definition 15.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . .
C8051F340/1/2/3/4/5/6/7 USB Register Definition 16.20. EINCSRH: USB0 IN Endpoint Control High Byte . . . 187 USB Register Definition 16.21. EOUTCSRL: USB0 OUT Endpoint Control Low Byte 189 USB Register Definition 16.22. EOUTCSRH: USB0 OUT Endpoint Control High Byte 190 USB Register Definition 16.23. EOUTCNTL: USB0 OUT Endpoint Count Low . . . . . 190 USB Register Definition 16.24. EOUTCNTH: USB0 OUT Endpoint Count High . . . . 190 SFR Definition 17.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . .
C8051F340/1/2/3/4/5/6/7 C2 Register Definition 23.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 279 C2 Register Definition 23.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 280 C2 Register Definition 23.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 280 C2 Register Definition 23.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 280 16 Rev. 0.
C8051F340/1/2/3/4/5/6/7 1. System Overview C8051F340/1/2/3/4/5/6/7 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection.
C8051F340/1/2/3/4/5/6/7 Supply Voltage Regulator SMBus/I2C Enhanced SPI UARTs Timers (16-bit) Programmable Counter Array External Memory Interface (EMIF) 10-bit 200ksps ADC Temperature Sensor Voltage Reference Analog Comparators 3 2 4 3 40 3 3 3 3 2 TQFP48 C8051F341-GQ 48 32k 2304 3 3 3 3 3 3 2 4 3 40 3 3 3 3 2 TQFP48 C8051F342-GQ 48 64k 4352 3 3 3 3 3 3 1 4 3 25 - 3 3 3 2 LQFP32 C8051F343-GQ 48 32k 2304 3 3 3 3 3 3 1 4 3 25 - 3 3 3 2 LQFP32 C80
C8051F340/1/2/3/4/5/6/7 C2D Port I/O Configuration Debug / Programming Hardware C2CK/RST UART0 Reset Power-On Reset Supply Monitor VDD Power Net VREG Voltage Regulator CIP-51 8051 Controller Core Timers 0, 1, 2, 3 Priority Crossbar Decoder PCA/WDT Port 3 Drivers P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Port 4 Drivers P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.
C8051F340/1/2/3/4/5/6/7 C2D Port I/O Configuration Debug / Programming Hardware C2CK/RST UART0 Reset Power-On Reset Supply Monitor VDD Power Net VREG Voltage Regulator Port 0 Drivers P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4 P0.5 P0.6/CNVSTR P0.7/VREF Port 1 Drivers P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Port 2 Drivers P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.
C8051F340/1/2/3/4/5/6/7 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F340/1/2/3/4/5/6/7 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software.
C8051F340/1/2/3/4/5/6/7 VDD Supply Monitor + - PCA WDT Software Reset (SWRSF) Errant FLASH Operation MCD Enable System Clock WDT Enable EN Internal LF Oscillator External Oscillator Drive Reset Funnel CIP-51 Microcontroller Core Enable EN XTAL2 (wired-OR) C0RSEF Missing Clock Detector (oneshot) XTAL1 '0' + - Px.x Clock Multiplier Power On Reset Comparator 0 Px.x Internal HF Oscillator Enable USB Controller System Reset Clock Select Extended Interrupt Handler Figure 1.3.
C8051F340/1/2/3/4/5/6/7 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indirect addressing.
C8051F340/1/2/3/4/5/6/7 1.3. Universal Serial Bus Controller The Universal Serial Bus Controller (USB0) is a USB 2.0 compliant Full or Low Speed function with integrated transceiver and endpoint FIFO RAM. A total of eight endpoint pipes are available: a bi-directional control endpoint (Endpoint0) and three pairs of IN/OUT endpoints (Endpoints1-3 IN/OUT). A 1k Byte block of RAM is used for USB FIFO space.
C8051F340/1/2/3/4/5/6/7 1.4. Voltage Regulator C8051F340/1/2/3/4/5/6/7 devices include a voltage regulator (REG0). When enabled, the REG0 output appears on the VDD pin, and can also be used to power other external devices. REG0 can be enabled/disabled by software. 1.5. On-Chip Debug Circuitry The C8051F340/1/2/3/4/5/6/7 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intrusive, full speed, in-circuit debugging of the production part installed in the end application.
C8051F340/1/2/3/4/5/6/7 1.6. Programmable Digital I/O and Crossbar C8051F340/1/4/5 devices include 40 I/O pins (five byte-wide Ports); C8051F342/3/6/7 devices include 25 I/O pins (three byte-wide Ports, and a 1-bit-wide Port). The C8051F340/1/2/3/4/5/6/7 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output.
C8051F340/1/2/3/4/5/6/7 1.7. Serial Ports The C8051F340/1/2/3/4/5/6/7 Family includes an SMBus/I2C interface, full-duplex UARTs, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. 1.8. Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers.
C8051F340/1/2/3/4/5/6/7 1.9. 10-Bit Analog to Digital Converter The C8051F340/1/2/3/4/5/6/7 devices include an on-chip 10-bit SAR ADC with a true differential input multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL of ±1LSB. The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC inputs. Twenty (48-pin package) or twenty-one (32-pin package) of the Port I/O pins can be used as analog inputs to the ADC.
C8051F340/1/2/3/4/5/6/7 1.10. Comparators C8051F340/1/2/3/4/5/6/7 devices include two on-chip voltage comparators that are enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output. Comparator response time is programmable, allowing the user to select between high-speed and low-power modes.
C8051F340/1/2/3/4/5/6/7 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings* Parameter Conditions Min Typ Max Units Ambient temperature under bias –55 125 °C Storage Temperature –65 150 °C Voltage on any Port I/O Pin or /RST with respect to GND –0.3 5.8 V Voltage on VDD with respect to GND –0.3 4.
C8051F340/1/2/3/4/5/6/7 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics –40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter Conditions Digital Supply Voltage1 Min Typ Max Units 2.7 3.3 3.6 V Digital Supply Current with CPU active VDD = 3.3 V, Clock = 24 MHz VDD = 3.3 V, Clock = 1 MHz VDD = 3.3 V, Clock = 32 kHz 15 0.7 74 mA mA µA Digital Supply Current with CPU active and USB active (Full or Low Speed) VDD = 3.
C8051F340/1/2/3/4/5/6/7 Table 3.2. Index to Electrical Characteristics Tables Page No.
C8051F340/1/2/3/4/5/6/7 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7 Name VDD Pin Numbers 48-pin 32-pin 10 6 Type Power In 2.7–3.6 V Power Supply Voltage Input. Power Out GND 7 3 /RST/ 13 9 C2CK Description 3.3 V Voltage Regulator Output. See Section 8. Ground. D I/O Device Reset. Open-drain output of internal POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at least 15 µs. See Section 11.
C8051F340/1/2/3/4/5/6/7 Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7 (Continued) Name 34 Pin Numbers 48-pin 32-pin Type Description P1.0 46 26 D I/O or Port 1.0. See Section 15 for a complete description of Port A In 1. P1.1 45 25 D I/O or Port 1.1. A In P1.2 44 24 D I/O or Port 1.2. A In P1.3 43 23 D I/O or Port 1.3. A In P1.4 42 22 D I/O or Port 1.4. A In P1.5 41 21 D I/O or Port 1.5. A In P1.6 40 20 D I/O or Port 1.6. A In P1.7 39 19 D I/O or Port 1.7.
C8051F340/1/2/3/4/5/6/7 Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7 (Continued) Name Pin Numbers 48-pin 32-pin Type Description P3.3 27 - D I/O or Port 3.3. A In P3.4 26 - D I/O or Port 3.4. A In P3.5 25 - D I/O or Port 3.5. A In P3.6 24 - D I/O or Port 3.6. A In P3.7 23 - D I/O or Port 3.7. A In P4.0 22 - D I/O or Port 4.0. See Section 15 for a complete description of Port A In 4. P4.1 21 - D I/O or Port 4.1. A In P4.2 20 - D I/O or Port 4.2. A In P4.
P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 48 47 46 45 44 43 42 41 40 39 38 37 C8051F340/1/2/3/4/5/6/7 P0.5 1 36 P2.2 P0.4 2 35 P2.3 P0.3 3 34 P2.4 P0.2 4 33 P2.5 P0.1 5 32 P2.6 P0.0 6 31 P2.7 GND 7 30 P3.0 D+ 8 29 P3.1 D- 9 28 P3.2 VDD 10 27 P3.3 REGIN 11 26 P3.4 VBUS 12 25 P3.5 20 21 22 23 24 P4.2 P4.1 P4.0 P3.7 P3.6 17 P4.5 19 16 P4.6 P4.3 15 P4.7 18 14 C2D P4.
C8051F340/1/2/3/4/5/6/7 D D1 Table 4.2. TQFP-48 Package Dimensions E1 E A A1 A2 b D D1 e E E1 MIN 0.05 0.95 0.17 - MM TYP 1.00 0.22 9.00 7.00 0.50 9.00 7.00 MAX 1.20 0.15 1.05 0.27 - 48 PIN 1 IDENTIFIER A2 1 e A b A1 Figure 4.2. TQFP-48 Package Diagram Rev. 0.
P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 32 31 30 29 28 27 26 25 C8051F340/1/2/3/4/5/6/7 P0.1 1 24 P1.2 P0.0 2 23 P1.3 GND 3 22 P1.4 D+ 4 21 P1.5 D- 5 20 P1.6 VDD 6 19 P1.7 REGIN 7 18 P2.0 VBUS 8 17 P2.1 9 10 11 12 13 14 15 16 /RST / C2CK P3.0 / C2D P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 C8051F342/3/6/7 Top View Figure 4.3. LQFP-32 Pinout Diagram (Top View) 38 Rev. 0.
C8051F340/1/2/3/4/5/6/7 D Table 4.3. LQFP-32 Package Dimensions D1 E1 E 32 PIN 1 IDENTIFIER A A1 A2 b D D1 e E E1 MIN 0.05 1.35 0.30 - MM TYP 1.40 0.37 9.00 7.00 0.80 9.00 7.00 MAX 1.60 0.15 1.45 0.45 - 1 A2 A b A1 e Figure 4.4. LQFP-32 Package Diagram Rev. 0.
C8051F340/1/2/3/4/5/6/7 NOTES: 40 Rev. 0.
C8051F340/1/2/3/4/5/6/7 5. 10-Bit ADC (ADC0) The ADC0 subsystem for the C8051F340/1/2/3/4/5/6/7 consists of two analog multiplexers (referred to collectively as AMUX0), and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector. The AMUX0, data conversion modes, and window detector are all configured under software control via the Special Function Registers shown in Figure 5.1.
C8051F340/1/2/3/4/5/6/7 5.1. Analog Multiplexer AMUX0 selects the positive and negative inputs to the ADC. The positive input (AIN+) can be connected to individual Port pins, the on-chip temperature sensor, or the positive power supply (VDD). The negative input (AIN-) can be connected to individual Port pins, VREF, or GND. When GND is selected as the negative input, ADC0 operates in Single-ended Mode; at all other times, ADC0 operates in Differential Mode.
C8051F340/1/2/3/4/5/6/7 5.2. Temperature Sensor The temperature sensor transfer function is shown in Figure 5.2. The output voltage (VTEMP) is the positive ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. Values for the Offset and Slope parameters can be found in Table 5.1. VTEMP = (Slope x TempC) + Offset Voltage TempC = (VTEMP - Offset) / Slope Slope (V / deg C) Offset (V at 0 Celsius) Temperature Figure 5.2.
Error (degrees C) C8051F340/1/2/3/4/5/6/7 5.0 0 5.0 0 4.0 0 4.0 0 3.0 0 3.0 0 2.0 0 2.0 0 1.0 0 1.0 0 0.0 0-40.00 -20.00 0.0 0 20.0 0 40.0 0 60.0 0 0.0 0 -1.00 -1.00 -2.00 -2.00 -3.00 -3.00 -4.00 -4.00 -5.00 -5.00 Temperature (degrees C) Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V) 44 80.0 0 Rev. 0.
C8051F340/1/2/3/4/5/6/7 5.3. Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + 1) for 0 ≤ AD0SC ≤ 31). 5.3.1. Starting a Conversion A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM2–0) in register ADC0CN.
C8051F340/1/2/3/4/5/6/7 5.3.2. Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal).
C8051F340/1/2/3/4/5/6/7 5.3.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion.
C8051F340/1/2/3/4/5/6/7 SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select R R R R/W R/W R/W R/W - - - AMX0P4 AMX0P3 AMX0P2 AMX0P1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 R/W Reset Value AMX0P0 00000000 Bit0 SFR Address: 0xBB Bits7–5: UNUSED. Read = 000b; Write = don’t care.
C8051F340/1/2/3/4/5/6/7 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select R R R R/W R/W R/W R/W - - - AMX0N4 AMX0N3 AMX0N2 AMX0N1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 R/W Reset Value AMX0N0 00000000 Bit0 SFR Address: 0xBA Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0N4–0: AMUX0 Negative Input Selection. Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended mode.
C8051F340/1/2/3/4/5/6/7 SFR Definition 5.3. ADC0CF: ADC0 Configuration R/W R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 AD0SC1 Bit7 Bit6 Bit5 Bit4 R/W R/W AD0SC0 AD0LJST Bit3 Bit2 R/W R/W Reset Value - - 11111000 Bit1 Bit0 SFR Address: 0xBC Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements are given in Table 5.1.
C8051F340/1/2/3/4/5/6/7 SFR Definition 5.6. ADC0CN: ADC0 Control R/W R/W AD0EN AD0TM Bit7 Bit6 R/W R/W R/W R/W AD0INT AD0BUSY AD0WINT AD0CM2 Bit5 Bit4 Bit3 R/W R/W Reset Value AD0CM1 AD0CM0 00000000 Bit2 Bit1 Bit0 (bit addressable) SFR Address: 0xE8 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions. Bit6: AD0TM: ADC0 Track Mode Bit.
C8051F340/1/2/3/4/5/6/7 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 conversion results to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in polled mode.
C8051F340/1/2/3/4/5/6/7 SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 00000000 0xC6 Bits7–0: High byte of ADC0 Less-Than Data Word. SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC5 Bits7–0: Low byte of ADC0 Less-Than Data Word. Rev. 0.
C8051F340/1/2/3/4/5/6/7 5.4.1. Window Detector In Single-Ended Mode Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer value.
C8051F340/1/2/3/4/5/6/7 5.4.2. Window Detector In Differential Mode Figure 5.8 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the measurable voltage between the input pins is between -VREF and VREF*(511/512). Output codes are represented as 10-bit 2’s complement signed integers.
C8051F340/1/2/3/4/5/6/7 Table 5.1. ADC0 Electrical Characteristics VDD = 3.0 V, VREF = 2.40 V, –40 to +85 °C unless otherwise specified Parameter Conditions Min Typ Max Units DC Accuracy Resolution 10 Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic bits ±0.5 ±1 LSB ±0.
C8051F340/1/2/3/4/5/6/7 6. Voltage Reference The Voltage reference MUX on C8051F340/1/2/3/4/5/6/7 devices is configurable to use an externally connected voltage reference, the on-chip reference voltage generator, or the power supply voltage VDD (see Figure 6.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For the internal reference or an external source, REFSL should be set to ‘0’; For VDD as the reference source, REFSL should be set to ‘1’.
C8051F340/1/2/3/4/5/6/7 SFR Definition 6.1. REF0CN: Reference Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - REFSL TEMPE BIASE REFBE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD1 Bits7–3: UNUSED. Read = 00000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF pin used as voltage reference. 1: VDD used as voltage reference. Bit2: TEMPE: Temperature Sensor Enable Bit.
C8051F340/1/2/3/4/5/6/7 7. Comparators C8051F340/1/2/3/4/5/6/7 devices include two on-chip programmable voltage Comparators. A block diagram of the comparators is shown in Figure 7.1, where “n” is the comparator number (0 or 1). The two Comparators operate identically with the following exceptions: (1) Their input selections differ, and (2) Comparator0 can be used as a reset source. For input selection details, refer to SFR Definition 7.2 and SFR Definition 7.5.
CMXnN2 CMXnN1 CMXnN0 CPTnCN CPTnMX C8051F340/1/2/3/4/5/6/7 CPnEN CPnOUT CPnRIF CPnFIF CPnHYP1 VDD CPn Interrupt CPnHYP0 CPnHYN1 CPnHYN0 CMXnP2 CMXnP1 CMXnP0 CPn Rising-edge CPn Falling-edge Interrupt Logic CPn + CPnRIE CPnFIE + D - SET CLR Q Q D SET CLR CPn Q Q Crossbar (SYNCHRONIZER) GND CPnA CPn - Port I/O connection options vary with package (32-pin or 48-pin) CPTnMD Reset Decision Tree (Comprator 0 Only) CPnRIE CPnFIE CPnMD1 CPnMD0 Figure 7.1.
C8051F340/1/2/3/4/5/6/7 VIN+ VIN- CP0+ CP0- + CP0 _ OUT CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS Negative Hysteresis Voltage (Programmed by CP0HYN Bits) VIN+ VOH OUTPUT VOL Negative Hysteresis Disabled Positive Hysteresis Disabled Maximum Negative Hysteresis Maximum Positive Hysteresis Figure 7.2. Comparator Hysteresis Plot Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN (shown in SFR Definition 7.
C8051F340/1/2/3/4/5/6/7 SFR Definition 7.1. CPT0CN: Comparator0 Control R/W R R/W R/W CP0EN CP0OUT CP0RIF CP0FIF Bit7 Bit6 Bit5 Bit4 R/W R/W R/W R/W Reset Value CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9B Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0–. 1: Voltage on CP0+ > CP0–. Bit5: CP0RIF: Comparator0 Rising-Edge Flag.
C8051F340/1/2/3/4/5/6/7 SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection R/W Bit7 R/W R/W R/W CMX0N2 CMX0N1 CMX0N0 Bit6 Bit5 Bit4 R/W R/W R/W - CMX0P2 CMX0P1 Bit3 Bit2 Bit1 R/W Reset Value CMX0P0 00000000 Bit0 SFR Address: 0x9F Bit7: UNUSED. Read = 0b, Write = don’t care. Bits6–4: CMX0N2–CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is used as the Comparator0 negative input.
C8051F340/1/2/3/4/5/6/7 SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection R/W R/W R/W R/W R/W R/W - - CP0RIE CP0FIE - - Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 R/W R/W Reset Value CP0MD1 CP0MD0 00000010 Bit1 Bit0 SFR Address: 0x9D Bits7–6: UNUSED. Read = 00b. Write = don’t care. Bit5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 rising-edge interrupt disabled. 1: Comparator0 rising-edge interrupt enabled. Bit4: CP0FIE: Comparator0 Falling-Edge Interrupt Enable.
C8051F340/1/2/3/4/5/6/7 SFR Definition 7.4. CPT1CN: Comparator1 Control R/W R R/W R/W CP1EN CP1OUT CP1RIF CP1FIF Bit7 Bit6 Bit5 Bit4 R/W R/W R/W R/W Reset Value CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9A Bit7: CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. Bit6: CP1OUT: Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1–. 1: Voltage on CP1+ > CP1–. Bit5: CP1RIF: Comparator1 Rising-Edge Flag.
C8051F340/1/2/3/4/5/6/7 SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection R/W Bit7 R/W R/W R/W CMX1N2 CMX1N1 CMX1N0 Bit6 Bit5 Bit4 R/W R/W R/W - CMX1P2 CMX1P1 Bit3 Bit2 Bit1 R/W Reset Value CMX1P0 00000000 Bit0 SFR Address: 0x9E Bit7: UNUSED. Read = 0b, Write = don’t care. Bits6–4: CMX1N2–CMX1N0: Comparator1 Negative Input MUX Select. These bits select which Port pin is used as the Comparator1 negative input.
C8051F340/1/2/3/4/5/6/7 SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection R/W R/W R/W R/W R/W R/W - - CP1RIE CP1FIE - - Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 R/W R/W Reset Value CP1MD1 CP1MD0 00000010 Bit1 Bit0 SFR Address: 0x9C Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP1RIE: Comparator1 Rising-Edge Interrupt Enable. 0: Comparator1 rising-edge interrupt disabled. 1: Comparator1 rising-edge interrupt enabled. Bit4: CP1FIE: Comparator1 Falling-Edge Interrupt Enable.
C8051F340/1/2/3/4/5/6/7 Table 7.1. Comparator Electrical Characteristics VDD = 3.0 V, –40 to +85 °C unless otherwise noted. All specifications apply to both Comparator0 and Comparator1 unless otherwise noted. Parameter Conditions Min Typ Max Units Response Time: Mode 0, Vcm* = 1.5 V CP0+ – CP0– = 100 mV 100 ns CP0+ – CP0– = –100 mV 250 ns Response Time: Mode 1, Vcm* = 1.5 V CP0+ – CP0– = 100 mV 175 ns CP0+ – CP0– = –100 mV 500 ns Response Time: Mode 2, Vcm* = 1.
C8051F340/1/2/3/4/5/6/7 8. Voltage Regulator (REG0) C8051F340/1/2/3/4/5/6/7 devices include a voltage regulator (REG0). When enabled, the REG0 output appears on the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by software using bit REGEN in register REG0CN. See Table 8.1 for REG0 electrical characteristics. Note that the VBUS signal must be connected to the VBUS pin when using the device in a USB network.
C8051F340/1/2/3/4/5/6/7 VBUS VBUS Sense From VBUS REGIN 5 V In Voltage Regulator (REG0) 3 V Out To 3 V Power Net Device Power Net VDD Figure 8.1. REG0 Configuration: USB Bus-Powered From VBUS VBUS VBUS Sense From 5 V Power Net REGIN 5 V In Voltage Regulator (REG0) 3 V Out To 3 V Power Net Device Power Net VDD Figure 8.2. REG0 Configuration: USB Self-Powered 70 Rev. 0.
C8051F340/1/2/3/4/5/6/7 From VBUS VBUS VBUS Sense REGIN 5 V In Voltage Regulator (REG0) 3 V Out From 3 V Power Net Device Power Net VDD Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled VBUS VBUS Sense From 5 V Power Net REGIN 5 V In Voltage Regulator (REG0) 3 V Out To 3 V Power Net Device Power Net VDD Figure 8.4. REG0 Configuration: No USB Connection Rev. 0.
C8051F340/1/2/3/4/5/6/7 SFR Definition 8.1. REG0CN: Voltage Regulator Control R/W R R/W REGDIS VBSTAT VBPOL Bit7 Bit6 Bit5 R/W R/W R/W R/W R/W Reset Value REGMOD Reserved Reserved Reserved Reserved 00000000 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC9 Bit7: REGDIS: Voltage Regulator Disable. 0: Voltage Regulator Enabled. 1: Voltage Regulator Disabled. Bit6: VBSTAT: VBUS Signal Status. 0: VBUS signal currently absent (device not attached to USB network).
C8051F340/1/2/3/4/5/6/7 9. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051.
C8051F340/1/2/3/4/5/6/7 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles.
C8051F340/1/2/3/4/5/6/7 CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. 9.1.2. MOVX Instruction and Program Memory The MOVX instruction is typically used to access external data memory (Note: the C8051F340/1/2/3/4/5/6/ 7 does not support off-chip data or program memory).
C8051F340/1/2/3/4/5/6/7 Table 9.1.
C8051F340/1/2/3/4/5/6/7 Table 9.1.
C8051F340/1/2/3/4/5/6/7 Notes on Registers, Operands and Addressing Modes: Rn - Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00-0x7F) or an SFR (0x80-0xFF).
C8051F340/1/2/3/4/5/6/7 9.2. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. The CIP-51 memory organization is shown in Figure 9.2.
C8051F340/1/2/3/4/5/6/7 9.2.2. Data Memory The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers.
C8051F340/1/2/3/4/5/6/7 9.2.6. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the MCU.
C8051F340/1/2/3/4/5/6/7 Table 9.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
C8051F340/1/2/3/4/5/6/7 Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
C8051F340/1/2/3/4/5/6/7 Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
C8051F340/1/2/3/4/5/6/7 9.2.7. Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sections of the datasheet associated with their corresponding system function.
C8051F340/1/2/3/4/5/6/7 SFR Definition 9.4. PSW: Program Status Word R/W R/W R/W R/W R/W R/W CY Bit7 R/W R AC F0 RS1 RS0 Bit6 Bit5 Bit4 Bit3 OV F1 PARITY 00000000 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Reset Value 0xD0 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to logic 0 by all other arithmetic operations.
C8051F340/1/2/3/4/5/6/7 SFR Definition 9.6. B: B Register R/W R/W R/W R/W R/W R/W R/W R/W B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Reset Value 0xF0 Bits7–0: B: B Register. This register serves as a second accumulator for certain arithmetic operations. 9.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting multiple interrupt sources with two priority levels.
C8051F340/1/2/3/4/5/6/7 IT0 1 1 0 0 IN0PL 0 1 0 1 /INT0 Interrupt Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive IT1 1 1 0 0 IN1PL 0 1 0 1 /INT1 Interrupt Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive /INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 9.13).
C8051F340/1/2/3/4/5/6/7 Bit addressable? Cleared by HW? Table 9.4. Interrupt Summary Enable Flag N/A N/A Always Enabled IE0 (TCON.1) Y Y EX0 (IE.0) PX0 (IP.0) 1 TF0 (TCON.5) Y Y ET0 (IE.1) PT0 (IP.1) 0x0013 2 IE1 (TCON.3) Y Y EX1 (IE.2) PX1 (IP.2) 0x001B 3 Y Y ET1 (IE.3) PT1 (IP.3) UART0 0x0023 4 Y N ES0 (IE.4) PS0 (IP.4) Timer 2 Overflow 0x002B 5 Y N ET2 (IE.5) PT2 (IP.5) SPI0 0x0033 6 TF1 (TCON.7) RI0 (SCON0.0) TI0 (SCON0.1) TF2H (TMR2CN.7) TF2L (TMR2CN.
C8051F340/1/2/3/4/5/6/7 SFR Definition 9.7. IE: Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W EA ESPI0 ET2 ES0 ET1 EX1 ET0 EX0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 90 Reset Value 0xA8 EA: Enable All Interrupts. This bit globally enables/disables all interrupts. It overrides the individual interrupt mask settings. 0: Disable all interrupt sources.
C8051F340/1/2/3/4/5/6/7 SFR Definition 9.8. IP: Interrupt Priority R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - PSPI0 PT2 PS0 PT1 PX1 PT0 PX0 10000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 0xB8 UNUSED. Read = 1, Write = don't care. PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt.
C8051F340/1/2/3/4/5/6/7 SFR Definition 9.9. EIE1: Extended Interrupt Enable 1 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value ET3 ECP1 ECP0 EPCA0 EADC0 EWADC0 EUSB0 ESMB0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE6 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 92 ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3L or TF3H flags.
C8051F340/1/2/3/4/5/6/7 SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value PT3 PCP1 PCP0 PPCA0 PADC0 PWADC0 PUSB0 PSMB0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF6 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: Timer 3 interrupts set to high priority level.
C8051F340/1/2/3/4/5/6/7 SFR Definition 9.11. EIE2: Extended Interrupt Enable 2 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - - - ES1 EVBUS 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE7 Bits7–2: UNUSED. Read = 000000b. Write = don’t care. Bit1: ES1: Enable UART1 Interrupt. This bit sets the masking of the UART1 interrupt. 0: Disable UART1 interrupt. 1: Enable UART1 interrupt. Bit0: EVBUS: Enable VBUS Level Interrupt.
C8051F340/1/2/3/4/5/6/7 SFR Definition 9.13. IT01CF: INT0/INT1 Configuration R/W R/W R/W R/W R/W R/W R/W R/W Reset Value IN1PL IN1SL2 IN1SL1 IN1SL0 IN0PL IN0SL2 IN0SL1 IN0SL0 00000001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE4 Note: Refer to SFR Definition 21.1 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 input is active high.
C8051F340/1/2/3/4/5/6/7 9.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all interrupts, are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states; the external oscillator is not affected).
C8051F340/1/2/3/4/5/6/7 SFR Definition 9.14. PCON: Power Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value GF5 GF4 GF3 GF2 GF1 GF0 STOP IDLE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x87 Bits7–2: GF5–GF0: General Purpose Flags 5–0. These are general purpose flags for use under software control. Bit1: STOP: Stop Mode Select. Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
C8051F340/1/2/3/4/5/6/7 NOTES: 98 Rev. 0.
C8051F340/1/2/3/4/5/6/7 10. Prefetch Engine The C8051F340/1/2/3/4/5/6/7 family of devices incorporate a 2-byte prefetch engine. Because the access time of the FLASH memory is 40 ns, and the minimum instruction time is roughly 20 ns, the prefetch engine is necessary for full-speed code execution. Instructions are read from FLASH memory two bytes at a time by the prefetch engine, and given to the CIP-51 processor core to execute.
C8051F340/1/2/3/4/5/6/7 NOTES: 100 Rev. 0.
C8051F340/1/2/3/4/5/6/7 11. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • • • • CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their defined reset values External Port pins are forced to a known state Interrupts and timers are disabled. All SFRs are reset to the predefined values noted in the SFR detailed descriptions.
C8051F340/1/2/3/4/5/6/7 11.1. Power-On Reset During power-up, the device is held in a reset state and the /RST pin is driven low until VDD settles above VRST. A Power-On Reset delay (TPORDelay) occurs before the device is released from reset; this delay is typically less than 0.3 ms. Figure 11.2. plots the power-on and VDD monitor reset timing. On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1.
C8051F340/1/2/3/4/5/6/7 11.2. Power-Fail Reset / VDD Monitor When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor will drive the /RST pin low and hold the CIP-51 in a reset state (see Figure 11.2). When VDD returns to a level above VRST, the CIP-51 will be released from the reset state.
C8051F340/1/2/3/4/5/6/7 11.3. External Reset The external /RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the /RST pin generates a reset; an external pull-up and/or decoupling of the / RST pin may be necessary to avoid erroneous noise-induced resets. See Table 11.1 for complete /RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset. 11.4.
C8051F340/1/2/3/4/5/6/7 11.8. Software Reset Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ following a software forced reset. The state of the /RST pin is unaffected by this reset. 11.9. USB Reset Writing ‘1’ to the USBRSF bit in register RSTSRC selects USB0 as a reset source. With USB0 selected as a reset source, a system reset will be generated when either of the following occur: 1. RESET signaling is detected on the USB network.
C8051F340/1/2/3/4/5/6/7 SFR Definition 11.2. RSTSRC: Reset Source R/W R R/W USBRSF FERROR C0RSEF Bit7 Bit6 Bit5 R/W SWRSF Bit4 R R/W WDTRSF MCDRSF Bit3 Bit2 R/W R Reset Value PORSF PINRSF Variable Bit1 Bit0 SFR Address: 0xEF Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: USBRSF: USB Reset Flag 0: Read: Last reset was not a USB reset; Write: USB resets disabled. 1: Read: Last reset was a USB reset; Write: USB resets enabled. FERROR: Flash Error Indicator.
C8051F340/1/2/3/4/5/6/7 Table 11.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter Conditions IOL = 8.5 mA, VDD = 2.7 to 3.6 V /RST Output Low Voltage /RST Input High Voltage /RST Input Low Voltage /RST Input Pull-Up Current VDD POR Threshold (VRST) Missing Clock Detector Timeout Reset Time Delay Min Typ Max 0.6 0.7 x VDD 2.40 25 2.55 0.3 x VDD 40 2.70 µA V 100 220 500 µs /RST = 0.
C8051F340/1/2/3/4/5/6/7 NOTES: 108 Rev. 0.
C8051F340/1/2/3/4/5/6/7 12. Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system through the C2 interface or by software using the MOVX instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. Flash bytes would typically be erased (set to 0xFF) before being reprogrammed.
C8051F340/1/2/3/4/5/6/7 12.1.3. Flash Write Procedure Bytes in Flash memory can be written one byte at a time, or in groups of two. The FLBWE bit in register PFE0CN (SFR Definition 10.1) controls whether a single byte or a block of two bytes is written to Flash during a write operation. When FLBWE is cleared to ‘0’, the Flash will be written one byte at a time. When FLBWE is set to ‘1’, the Flash will be written in two-byte blocks.
C8051F340/1/2/3/4/5/6/7 Table 12.1. Flash Electrical Characteristics Parameter Flash Size Endurance Erase Cycle Time Write Cycle Time Conditions C8051F340/2/4/6* Min 65536* C8051F341/3/5/7 32768 20k 10 40 25 MHz System Clock 25 MHz System Clock Typ 100k 15 55 Max 20 70 Units Bytes Bytes Erase/Write ms µs *Note: 1024 bytes at location 0xFC00 to 0xFFFF are reserved. 12.2. Non-volatile Data Storage The Flash memory can be used for non-volatile data storage as well as program code.
C8051F340/1/2/3/4/5/6/7 C8051F340/2/4/6 Reserved 0xFC00 Lock Byte 0xFBFF 0xFBFE 0xFA00 FLASH memory organized in 512-byte pages Locked when any other FLASH pages are locked C8051F341/3/5/7 Lock Byte Unlocked FLASH Pages Access limit set according to the FLASH security lock byte Unlocked FLASH Pages 0x0000 0x0000 Figure 12.1. Flash Program Memory Map and Security Byte 112 0x7FFF 0x7FFE 0x7E00 Rev. 0.
C8051F340/1/2/3/4/5/6/7 The level of FLASH security depends on the FLASH access method. The three FLASH access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. Accessing FLASH from the C2 debug interface: 1. 2. 3. 4. 5. 6. Any unlocked page may be read, written, or erased. Locked pages cannot be read, written, or erased.
C8051F340/1/2/3/4/5/6/7 SFR Definition 12.1. PSCTL: Program Store R/W Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - - Reserved PSEE PSWE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x8F Bits7–3: Unused: Read = 00000b. Write = don’t care. Bit2: Reserved. Read = 0b. Must Write = 0b. Bit1: PSEE: Program Store Erase Enable Setting this bit (in combination with PSWE) allows an entire page of Flash program memory to be erased.
C8051F340/1/2/3/4/5/6/7 SFR Definition 12.3. FLSCL: Flash Scale R/W FOSE Bit7 R/W R/W Reserved Reserved Bit6 Bit5 R/W FLRT Bit4 R/W R/W R/W R/W Reset Value Reserved Reserved Reserved Reserved 10000000 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB6 Bits7: FOSE: Flash One-shot Enable This bit enables the Flash read one-shot. When the Flash one-shot disabled, the Flash sense amps are enabled for a full clock cycle during Flash reads.
C8051F340/1/2/3/4/5/6/7 NOTES: 116 Rev. 0.
C8051F340/1/2/3/4/5/6/7 13. External Data Memory Interface and On-Chip XRAM 4k Bytes (C8051F340/2/4/6) or 2k Bytes (C8051F341/3/5/7) of RAM are included on-chip, and mapped into the external data memory space (XRAM). The 1k Bytes of USB FIFO space can also be mapped into XRAM address space for additional general-purpose data storage.
C8051F340/1/2/3/4/5/6/7 13.2. Accessing USB FIFO Space The C8051F340/1/2/3/4/5/6/7 include 1k of RAM which functions as USB FIFO space. Figure 13.1 shows an expanded view of the FIFO space and user XRAM. FIFO space is normally accessed via USB FIFO registers; see Section “16.5. FIFO Management” on page 171 for more information on accessing these FIFOs. The MOVX instruction should not be used to load or modify USB data in the FIFO space.
C8051F340/1/2/3/4/5/6/7 13.3. Configuring the External Memory Interface Configuring the External Memory Interface consists of five steps: 1. Configure the Output Modes of the associated port pins as either push-pull or open-drain (push-pull is most common), and skip the associated pins in the crossbar. 2. Configure Port latches to “park” the EMIF pins in a dormant state (usually by setting them to logic ‘1’). 3. Select Multiplexed mode or Non-multiplexed mode. 4.
C8051F340/1/2/3/4/5/6/7 SFR Definition 13.1. EMI0CN: External Memory Interface Control R/W R/W R/W R/W R/W R/W R/W PGSEL7 PGSEL6 PGSEL5 PGSEL4 PGSEL3 PGSEL2 PGSEL1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 R/W Reset Value PGSEL0 00000000 Bit0 SFR Address: 0xAA Bits7–0: PGSEL[7:0]: XRAM Page Select Bits. The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM.
C8051F340/1/2/3/4/5/6/7 SFR Definition 13.2. EMI0CF: External Memory Configuration R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - USBFAE - EMD2 EMD1 EMD0 EALE1 EALE0 00000011 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x85 Bit7: Bit6: Unused. Read = 0b. Write = don’t care. USBFAE: USB FIFO Access Enable. 0: USB FIFO RAM not available through MOVX instructions. 1: USB FIFO RAM available using MOVX instructions.
C8051F340/1/2/3/4/5/6/7 13.5. Multiplexed and Non-multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit. 13.5.1. Multiplexed Configuration In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins: AD[7:0]. In this mode, an external latch (74HC373 or equivalent logic gate) is used to hold the lower 8-bits of the RAM address.
C8051F340/1/2/3/4/5/6/7 13.5.2. Non-multiplexed Configuration In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non-multiplexed Configuration is shown in Figure 13.3. See Section “13.7.1. Non-multiplexed Mode” on page 127 for more information about Non-multiplexed operation. E M I F A[15:0] ADDRESS BUS A[15:0] VDD (Optional) 64K X 8 SRAM I/O[7:0] 8 D[7:0] DATA BUS CE WE OE /WR /RD Figure 13.3. Non-multiplexed Configuration Example 13.6.
C8051F340/1/2/3/4/5/6/7 13.6.1. Internal XRAM Only When EMI0CF.[3:2] are set to ‘00’, all MOVX instructions will target the internal XRAM space on the device. Memory accesses to addresses beyond the populated space will wrap on 2k or 4k boundaries (depending on the RAM available on the device). As an example, the addresses 0x1000 and 0x2000 both evaluate to address 0x0000 in on-chip XRAM space.
C8051F340/1/2/3/4/5/6/7 13.6.3. Split Mode with Bank Select When EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas, on-chip space and off-chip space. • • • • Effective addresses below the internal XRAM size boundary will access on-chip XRAM space. Effective addresses above the internal XRAM size boundary will access off-chip space. 8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-chip or off-chip.
C8051F340/1/2/3/4/5/6/7 SFR Definition 13.3. EMI0TC: External Memory Timing Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value EAS1 EAS0 ERW3 EWR2 EWR1 EWR0 EAH1 EAH0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x84 Bits7–6: EAS1–0: EMIF Address Setup Time Bits. 00: Address setup time = 0 SYSCLK cycles. 01: Address setup time = 1 SYSCLK cycle. 10: Address setup time = 2 SYSCLK cycles. 11: Address setup time = 3 SYSCLK cycles.
C8051F340/1/2/3/4/5/6/7 13.7.1. Non-multiplexed Mode 13.7.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’. Nonmuxed 16-bit WRITE ADDR[15:8] P2 EMIF ADDRESS (8 MSBs) from DPH P2 ADDR[7:0] P3 EMIF ADDRESS (8 LSBs) from DPL P3 DATA[7:0] P4 EMIF WRITE DATA P4 T T WDS T ACS WDH T T ACW ACH /WR P1.7 P1.7 /RD P1.6 P1.
C8051F340/1/2/3/4/5/6/7 13.7.1.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’. Nonmuxed 8-bit WRITE without Bank Select ADDR[15:8] P2 ADDR[7:0] P3 EMIF ADDRESS (8 LSBs) from R0 or R1 P3 DATA[7:0] P4 EMIF WRITE DATA P4 T T WDS T WDH T ACS T ACW ACH /WR P1.7 P1.7 /RD P1.6 P1.
C8051F340/1/2/3/4/5/6/7 13.7.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’. Muxed 8-bit WRITE with Bank Select ADDR[15:8] P3 AD[7:0] P4 EMIF ADDRESS (8 MSBs) from EMI0CN EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH ALE P3 EMIF WRITE DATA P4 T ALEL P1.3 P1.3 T T WDS T ACS WDH T T ACW ACH /WR P1.7 P1.7 /RD P1.6 P1.
C8051F340/1/2/3/4/5/6/7 13.7.2. Multiplexed Mode 13.7.2.1.16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’. Muxed 16-bit WRITE ADDR[15:8] P3 AD[7:0] P4 EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS (8 LSBs) from DPL T ALEH ALE P3 EMIF WRITE DATA P4 T ALEL P1.3 P1.3 T T WDS T ACS WDH T T ACW ACH /WR P1.7 P1.7 /RD P1.6 P1.
C8051F340/1/2/3/4/5/6/7 13.7.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’. Muxed 8-bit WRITE Without Bank Select ADDR[15:8] AD[7:0] P3 P4 EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH ALE EMIF WRITE DATA P4 T ALEL P1.3 P1.3 T T WDS T ACS WDH T T ACW ACH /WR P1.7 P1.7 /RD P1.6 P1.6 Muxed 8-bit READ Without Bank Select ADDR[15:8] AD[7:0] P3 P4 EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH ALE EMIF READ DATA T T ALEL RDS P4 T RDH P1.3 P1.
C8051F340/1/2/3/4/5/6/7 13.7.2.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’. Muxed 8-bit WRITE with Bank Select ADDR[15:8] P3 AD[7:0] P4 EMIF ADDRESS (8 MSBs) from EMI0CN EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH ALE P3 EMIF WRITE DATA P4 T ALEL P1.3 P1.3 T T WDS T ACS WDH T T ACW ACH /WR P1.7 P1.7 /RD P1.6 P1.
C8051F340/1/2/3/4/5/6/7 Table 13.1.
C8051F340/1/2/3/4/5/6/7 NOTES: 134 Rev. 0.
C8051F340/1/2/3/4/5/6/7 14. Oscillators C8051F340/1/2/3/4/5/6/7 devices include a programmable internal high-frequency oscillator, a programmable internal low-frequency oscillator (C8051F340/1/2/3/4/5), an external oscillator drive circuit, and a 4x Clock Multiplier. The internal high-frequency and low-frequency oscillators can be enabled/disabled and adjusted using the special function registers, as shown in Figure 14.1.
C8051F340/1/2/3/4/5/6/7 14.1. Programmable Internal High-Frequency (H-F) Oscillator All C8051F340/1/2/3/4/5/6/7 devices include a programmable internal oscillator that defaults as the system clock after a system reset. The internal oscillator period can be programmed via the OSCICL register shown in SFR Definition 14.2. The OSCICL register is factory calibrated to obtain a 12 MHz internal oscillator frequency. Electrical specifications for the precision internal oscillator are given in Table 14.
C8051F340/1/2/3/4/5/6/7 SFR Definition 14.2. OSCICL: Internal H-F Oscillator Calibration R/W R/W R/W - - - Bit7 Bit6 Bit5 R/W R/W Bit4 Bit3 R/W R/W R/W Reset Value Bit1 Bit0 SFR Address: OSCCAL Bit2 Variable 0xB3 Bits4–0: OSCCAL: Oscillator Calibration Value These bits determine the internal H-F oscillator period. When set to 00000b, the oscillator operates at its fastest setting. When set to 11111b, the oscillator operates at is slowest setting.
C8051F340/1/2/3/4/5/6/7 SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control R/W R R/W OSCLEN OSCLRDY OSCLF3 Bit7 Bit6 Bit5 R R/W R/W R/W R/W Reset Value OSCLF2 OSCLF1 OSCLF0 OSCLD1 OSCLD0 00vvvv00 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x86 Bit7: OSCLEN: Internal L-F Oscillator Enable. 0: Internal L-F Oscillator Disabled. 1: Internal L-F Oscillator Enabled. Bit6: OSCLRDY: Internal L-F Oscillator Ready Flag. 0: Internal L-F Oscillator frequency not stabilized.
C8051F340/1/2/3/4/5/6/7 14.3. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/ resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 14.1. A 10 MΩ resistor also must be wired across the XTAL1 and XTAL2 pins for the crystal/resonator configuration.
C8051F340/1/2/3/4/5/6/7 14.3.3. External RC Example If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 14.1, Option 2. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout.
C8051F340/1/2/3/4/5/6/7 SFR Definition 14.4. OSCXCN: External Oscillator Control R R/W R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit4 R R/W R/W R/W Reset Value - XFCN2 XFCN1 XFCN0 00000000 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB1 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal Oscillator is running and stable. Bits6–4: XOSCMD2–0: External Oscillator Mode Bits.
C8051F340/1/2/3/4/5/6/7 14.4. 4x Clock Multiplier The 4x Clock Multiplier allows a 12 MHz oscillator to generate the 48 MHz clock required for Full Speed USB communication (see Section “16.4. USB Clock Configuration” on page 170). A divided version of the Multiplier output can also be used as the system clock. See Section 14.5 for details on system clock and USB clock source selection. The 4x Clock Multiplier is configured via the CLKMUL register.
C8051F340/1/2/3/4/5/6/7 14.5. System and USB Clock Selection The internal oscillator requires little start-up time and may be selected as the system or USB clock immediately following the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typically require a start-up time before they are settled and ready for use. The Crystal Valid Flag (XTLVLD in register OSCXCN) is set to ‘1’ by hardware when the external oscillator is settled.
C8051F340/1/2/3/4/5/6/7 SFR Definition 14.6. CLKSEL: Clock Select R/W R/W Bit7 R/W R/W R/W Bit4 Bit3 USBCLK Bit6 Bit5 R/W - R/W R/W Reset Value Bit0 SFR Address CLKSL Bit2 Bit1 00000000 0xA9 Bit 7: Unused. Read = 0b; Write = don’t care. Bits6–4: USBCLK2–0: USB Clock Select These bits select the clock supplied to USB0. When operating USB0 in full-speed mode, the selected clock should be 48 MHz. When operating USB0 in low-speed mode, the selected clock should be 6 MHz.
C8051F340/1/2/3/4/5/6/7 Table 14.1. Oscillator Electrical Characteristics VDD = 2.7 to 3.6 V; –40 to +85 °C unless otherwise specified Parameter Conditions Min Typ Max Units 11.82 12.00 12.18 MHz — 685 — µA 72 80 99 kHz — 7.0 — µA Full Speed Mode 47.88 48 48.12 Low Speed Mode 5.91 6 6.09 Internal High-Frequency Oscillator (Using Factory-Calibrated Settings) Oscillator Frequency Oscillator Supply Current (from VDD) IFCN = 11b 24 ºC, VDD = 3.0 V, OSCICN.
C8051F340/1/2/3/4/5/6/7 NOTES: 146 Rev. 0.
C8051F340/1/2/3/4/5/6/7 15. Port Input/Output Digital and analog resources are available through 40 I/O pins (C8051F340/1/4/5) or 25 I/O pins (C8051F342/3/6/7). Port pins are organized as shown in Figure 15.1. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input; Port pins P0.0-P3.7 can be assigned to one of the internal digital resources as shown in Figure 15.3.
C8051F340/1/2/3/4/5/6/7 /WEAK-PULLUP VDD PUSH-PULL /PORT-OUTENABLE VDD (WEAK) PORT PAD PORT-OUTPUT GND Analog Select ANALOG INPUT PORT-INPUT Figure 15.2. Port I/O Cell Block Diagram 148 Rev. 0.
C8051F340/1/2/3/4/5/6/7 15.1. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 15.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips that pin when assigning the next selected resource.
C8051F340/1/2/3/4/5/6/7 7 0 1 2 /RD 6 /WR 5 VREF 4 P3 P3.1-P3.
C8051F340/1/2/3/4/5/6/7 15.2. Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register (PnMDOUT). Step 3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP). Step 4. Assign Port pins to desired peripherals (XBR0, XBR1).
C8051F340/1/2/3/4/5/6/7 SFR Definition 15.1. XBR0: Port I/O Crossbar Register 0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value CP1AE CP1E CP0AE CP0E SYSCKE SMB0E SPI0E URT0E 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE1 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 152 CP1AE: Comparator1 Asynchronous Output Enable 0: Asynchronous CP1 unavailable at Port pin. 1: Asynchronous CP1 routed to Port pin.
C8051F340/1/2/3/4/5/6/7 SFR Definition 15.2. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W R/W R/W WEAKPUD XBARE T1E T0E ECIE Bit7 Bit6 Bit5 Bit4 Bit3 R/W R/W R/W Reset Value Bit0 SFR Address: PCA0ME Bit2 Bit1 00000000 0xE2 Bit7: WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-ups enabled (except for Ports whose I/O are configured as analog input or push-pull output). 1: Weak Pull-ups disabled. Bit6: XBARE: Crossbar Enable. 0: Crossbar disabled; all Port drivers disabled.
C8051F340/1/2/3/4/5/6/7 15.3. General Purpose Port I/O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general purpose I/O. Ports 3-0 are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. Port 4 (C8051F340/1/4/5 only) uses an SFR which is byte-addressable. When writing to a Port, the value written to the SFR is latched to maintain the output data value at each pin.
C8051F340/1/2/3/4/5/6/7 SFR Definition 15.6. P0MDOUT: Port0 Output Mode R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA4 Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in register P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull.
C8051F340/1/2/3/4/5/6/7 SFR Definition 15.8. P1: Port1 Latch R/W R/W R/W R/W R/W R/W R/W R/W P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Reset Value 0x90 Bits7–0: P1.[7:0] Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’). 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0).
C8051F340/1/2/3/4/5/6/7 SFR Definition 15.11. P1SKIP: Port1 Skip R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD5 Bits7–0: P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P1.
C8051F340/1/2/3/4/5/6/7 SFR Definition 15.14. P2MDOUT: Port2 Output Mode R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA6 Bits7–0: Output Configuration Bits for P2.7–P2.0 (respectively): ignored if corresponding bit in register P2MDIN is logic 0. 0: Corresponding P2.n Output is open-drain. 1: Corresponding P2.n Output is push-pull. SFR Definition 15.15.
C8051F340/1/2/3/4/5/6/7 SFR Definition 15.16. P3: Port3 Latch R/W R/W R/W R/W R/W R/W R/W R/W P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Reset Value 0xB0 Bits7–0: P3.[7:0] Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P3MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P3MDIN.
C8051F340/1/2/3/4/5/6/7 SFR Definition 15.19. P3SKIP: Port3 Skip R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xDF Bits7–0: P3SKIP[3:0]: Port3 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P3.
C8051F340/1/2/3/4/5/6/7 SFR Definition 15.21. P4MDIN: Port4 Input Mode R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF5 Bits7–0: Analog Input Configuration Bits for P4.7–P4.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P4.n pin is configured as an analog input. 1: Corresponding P4.n pin is not configured as an analog input.
C8051F340/1/2/3/4/5/6/7 Table 15.1. Port I/O DC Electrical Characteristics VDD = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified Parameters Conditions Min IOH = –3 mA, Port I/O push-pull VDD – 0.7 Output High Voltage IOH = –10 µA, Port I/O push-pull V 0.6 IOL = 10 µA 0.1 V 1.0 Input High Voltage Input Low Voltage 162 Units VDD – 0.8 IOL = 25 mA Input Leakage Current Max VDD – 0.1 IOH = –10 mA, Port I/O push-pull IOL = 8.5 mA Output Low Voltage Typ 2.0 0.
C8051F340/1/2/3/4/5/6/7 16. Universal Serial Bus Controller (USB0) C8051F340/1/2/3/4/5/6/7 devices include a complete Full/Low Speed USB function for USB peripheral implementations*. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching resistors and configurable pull-up resistors), 1k FIFO block, and clock recovery mechanism for crystal-less operation. No external components are required.
C8051F340/1/2/3/4/5/6/7 16.1. Endpoint Addressing A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bi-directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint pipes: Table 16.1.
C8051F340/1/2/3/4/5/6/7 SFR Definition 16.1. USB0XCN: USB0 Transceiver Control R/W R/W R/W PREN PHYEN SPEED Bit7 Bit6 Bit5 R/W R/W PHYTST1 PHYTST0 Bit4 R R R Reset Value DFREC Dp Dn 00000000 Bit2 Bit1 Bit0 SFR Address: Bit3 0xD7 Bit7: PREN: Internal Pull-up Resistor Enable The location of the pull-up resistor (D+ or D–) is determined by the SPEED bit. 0: Internal pull-up resistor disabled (device effectively detached from the USB network).
C8051F340/1/2/3/4/5/6/7 16.3. USB Register Access The USB0 controller registers listed in Table 16.2 are accessed through two SFRs: USB0 Address (USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted by reads/writes of the USB0DAT register. See Figure 16.2. Endpoint control/status registers are accessed by first writing the USB register INDEX with the target endpoint number.
C8051F340/1/2/3/4/5/6/7 SFR Definition 16.2. USB0ADR: USB0 Indirect Address R/W R/W BUSY AUTORD Bit7 Bit6 R/W R/W R/W Bit5 Bit4 Bit3 R/W R/W R/W Reset Value Bit1 Bit0 SFR Address: USBADDR Bit2 00000000 0x96 Bits7: BUSY: USB0 Register Read Busy Flag This bit is used during indirect USB0 register accesses. Software should write ‘1’ to this bit to initiate a read of the USB0 register targeted by the USBADDR bits (USB0ADR.[5-0]).
C8051F340/1/2/3/4/5/6/7 SFR Definition 16.3. USB0DAT: USB0 Data R/W R/W R/W R/W Bit7 Bit6 Bit5 Bit4 R/W R/W R/W R/W Reset Value Bit2 Bit1 Bit0 SFR Address: USB0DAT Bit3 00000000 0x97 This SFR is used to indirectly read and write USB0 registers. Write Procedure: 1. Poll for BUSY (USB 0ADR.7) => ‘0’. 2. Load the target USB0 register address into the USBADDR bits in register USB0ADR. 3. Write data to USB0DAT. 4. Repeat (Step 2 may be skipped when writing to the same USB0 register).
C8051F340/1/2/3/4/5/6/7 Table 16.2.
C8051F340/1/2/3/4/5/6/7 16.4. USB Clock Configuration USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock must be 6 MHz. When operating as a Full Speed function, the USB0 clock must be 48 MHz. Clock options are described in Section “14. Oscillators” on page 135. The USB0 clock is selected via SFR CLKSEL (see SFR Definition 14.6).
C8051F340/1/2/3/4/5/6/7 16.5. FIFO Management 1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between Endpoints0-3 as shown in Figure 16.3. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT, or both (Split Mode: half IN, half OUT).
C8051F340/1/2/3/4/5/6/7 16.5.2. FIFO Double Buffering FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum packet size is halved and the FIFO may contain two packets at a time. This mode is available for Endpoints1-3. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN Endpoint and/or the OUT endpoint. When Split Mode is not enabled, double-buffering may be enabled for the entire endpoint FIFO. See Table 16.
C8051F340/1/2/3/4/5/6/7 16.6. Function Addressing The FADDR register holds the current USB0 function address. Software should write the host-assigned 7-bit function address to the FADDR register when received as part of a SET_ADDRESS command. A new address written to FADDR will not take effect (USB0 will not respond to the new address) until the end of the current transfer (typically following the status phase of the SET_ADDRESS command transfer). The UPDATE bit (FADDR.
C8051F340/1/2/3/4/5/6/7 “14. Oscillators” on page 135 for more details on internal oscillator configuration, including the Suspend mode feature of the internal oscillator. USB0 exits Suspend mode when any of the following occur: (1) Resume signaling is detected or generated, (2) Reset signaling is detected, or (3) a device or USB reset occurs. If suspended, the internal oscillator will exit Suspend mode upon any of the above listed events.
C8051F340/1/2/3/4/5/6/7 USB Register Definition 16.8. POWER: USB0 Power R/W R/W R/W R/W ISOUD - - USBINH Bit7 Bit6 Bit5 Bit4 R/W R/W USBRST RESUME Bit3 Bit2 R R/W Reset Value SUSMD SUSEN 00010000 Bit1 Bit0 USB Address: 0x01 Bit7: ISOUD: ISO Update This bit affects all IN Isochronous endpoints. 0: When software writes INPRDY = ‘1’, USB0 will send the packet when the next IN token is received.
C8051F340/1/2/3/4/5/6/7 USB Register Definition 16.9. FRAMEL: USB0 Frame Number Low R R R R R R R R Frame Number Low Bit7 Bit6 Bit5 Bit4 Bit3 Reset Value 00000000 Bit2 Bit1 Bit0 USB Address: 0x0C Bits7-0: Frame Number Low This register contains bits7-0 of the last received frame number. USB Register Definition 16.10.
C8051F340/1/2/3/4/5/6/7 USB Register Definition 16.11. IN1INT: USB0 IN Endpoint Interrupt R R R R R R R R Reset Value - - - - IN3 IN2 IN1 EP0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x02 Bits7–4: Unused. Read = 0000b. Write = don’t care. Bit3: IN3: IN Endpoint 3 Interrupt-pending Flag This bit is cleared when software reads the IN1INT register. 0: IN Endpoint 3 interrupt inactive. 1: IN Endpoint 3 interrupt active.
C8051F340/1/2/3/4/5/6/7 USB Register Definition 16.13. CMINT: USB0 Common Interrupt R R R R R R R R Reset Value - - - - SOF RSTINT RSUINT SUSINT 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x06 Bits7–4: Unused. Read = 0000b; Write = don’t care. Bit3: SOF: Start of Frame Interrupt Set by hardware when a SOF token is received.
C8051F340/1/2/3/4/5/6/7 USB Register Definition 16.14. IN1IE: USB0 IN Endpoint Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - IN3E IN2E IN1E EP0E 00001111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x07 Bits7–4: Unused. Read = 0000b. Write = don’t care. Bit3: IN3E: IN Endpoint 3 Interrupt Enable 0: IN Endpoint 3 interrupt disabled. 1: IN Endpoint 3 interrupt enabled. Bit2: IN2E: IN Endpoint 2 Interrupt Enable 0: IN Endpoint 2 interrupt disabled.
C8051F340/1/2/3/4/5/6/7 USB Register Definition 16.16. CMIE: USB0 Common Interrupt Enable R/W R/W R/W R/W R/W - - - - SOFE Bit7 Bit6 Bit5 Bit4 Bit3 R/W R/W R/W Reset Value RSTINTE RSUINTE SUSINTE 00000110 Bit2 Bit1 Bit0 USB Address: 0x0B Bits7–4: Unused. Read = 0000b; Write = don’t care. Bit3: SOFE: Start of Frame Interrupt Enable 0: SOF interrupt disabled. 1: SOF interrupt enabled. Bit2: RSTINTE: Reset Interrupt Enable 0: Reset interrupt disabled. 1: Reset interrupt enabled.
C8051F340/1/2/3/4/5/6/7 The E0CNT register (USB Register Definition 16.18) holds the number of received data bytes in the Endpoint0 FIFO. Hardware will automatically detect protocol errors and send a STALL condition in response. Firmware may force a STALL condition to abort the current transfer. When a STALL condition is generated, the STSTL bit will be set to ‘1’ and an interrupt generated. The following conditions will cause hardware to generate a STALL condition: 1.
C8051F340/1/2/3/4/5/6/7 16.10.3.Endpoint0 OUT Transactions When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware will set the OPRDY bit (E0CSR.0) to ‘1’ and generate an Endpoint0 interrupt. Following this interrupt, firmware should unload the OUT packet from the Endpoint0 FIFO and set the SOPRDY bit (E0CSR.6) to ‘1’.
C8051F340/1/2/3/4/5/6/7 USB Register Definition 16.17. E0CSR: USB0 Endpoint0 Control R/W R/W SSUEND SOPRDY Bit7 Bit6 R/W SDSTL Bit5 R R/W SUEND DATAEND Bit4 Bit3 R/W R/W R Reset Value STSTL INPRDY OPRDY 00000000 Bit2 Bit1 Bit0 USB Address: 0x11 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: SSUEND: Serviced Setup End Write: Software should set this bit to ‘1’ after servicing a Setup End (bit SUEND) event. Hardware clears the SUEND bit when software writes ‘1’ to SSUEND.
C8051F340/1/2/3/4/5/6/7 USB Register Definition 16.18. E0CNT: USB0 Endpoint 0 Data Count R R R R - R R R R E0CNT Bit7 Bit6 Bit5 Bit4 Bit3 Reset Value 00000000 Bit2 Bit1 Bit0 USB Address: 0x16 Bit7: Unused. Read = 0; Write = don’t care. Bits6–0: E0CNT: Endpoint 0 Data Count This 7-bit number indicates the number of received data bytes in the Endpoint 0 FIFO. This number is only valid while bit OPRDY is a ‘1’. 16.11.
C8051F340/1/2/3/4/5/6/7 Writing ‘1’ to INPRDY without writing any data to the endpoint FIFO will cause a zero-length packet to be transmitted upon reception of the next IN token. A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EINCSRL.4). While SDSTL = ‘1’, hardware will respond to all IN requests with a STALL condition. Each time hardware generates a STALL condition, an interrupt will be generated and the STSTL bit (EINCSRL.5) set to ‘1’.
C8051F340/1/2/3/4/5/6/7 USB Register Definition 16.19. EINCSRL: USB0 IN Endpoint Control Low Byte R W R/W R/W R/W - CLRDT STSTL SDSTL FLUSH Bit7 Bit6 Bit5 Bit4 Bit3 R/W R/W UNDRUN FIFONE Bit2 Bit1 R/W Reset Value INPRDY 00000000 Bit0 USB Address: 0x11 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 186 Unused. Read = 0; Write = don’t care. CLRDT: Clear Data Toggle. Write: Software should write ‘1’ to this bit to reset the IN Endpoint data toggle to ‘0’.
C8051F340/1/2/3/4/5/6/7 USB Register Definition 16.20. EINCSRH: USB0 IN Endpoint Control High Byte R/W R/W R/W R R/W R/W R R Reset Value DBIEN ISO DIRSEL - FCDT SPLIT - - 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x12 Bit7: DBIEN: IN Endpoint Double-buffer Enable. 0: Double-buffering disabled for the selected IN endpoint. 1: Double-buffering enabled for the selected IN endpoint. Bit6: ISO: Isochronous Transfer Enable.
C8051F340/1/2/3/4/5/6/7 A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EOUTCSRL.5). While SDSTL = ‘1’, hardware will respond to all OUT requests with a STALL condition. Each time hardware generates a STALL condition, an interrupt will be generated and the STSTL bit (EOUTCSRL.6) set to ‘1’. The STSTL bit must be reset to ‘0’ by firmware. Hardware will automatically set OPRDY when a packet is ready in the OUT FIFO.
C8051F340/1/2/3/4/5/6/7 USB Register Definition 16.21. EOUTCSRL: USB0 OUT Endpoint Control Low Byte W R/W R/W R/W R R/W R R/W Reset Value CLRDT STSTL SDSTL FLUSH DATERR OVRUN FIFOFUL OPRDY 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x14 Bit7: Bit6: Bit5: Bit4: CLRDT: Clear Data Toggle Write: Software should write ‘1’ to this bit to reset the OUT endpoint data toggle to ‘0’. Read: This bit always reads ‘0’.
C8051F340/1/2/3/4/5/6/7 USB Register Definition 16.22. EOUTCSRH: USB0 OUT Endpoint Control High Byte R/W R/W R/W R/W R R R R Reset Value DBOEN ISO - - - - - - 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address: 0x15 Bit7: DBOEN: Double-buffer Enable 0: Double-buffering disabled for the selected OUT endpoint. 1: Double-buffering enabled for the selected OUT endpoint.
C8051F340/1/2/3/4/5/6/7 Table 16.4. USB Transceiver Electrical Characteristics VDD = 3.0 to 3.
C8051F340/1/2/3/4/5/6/7 NOTES: 192 Rev. 0.
C8051F340/1/2/3/4/5/6/7 17. SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data.
C8051F340/1/2/3/4/5/6/7 17.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: 1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. 2. The I2C-Bus Specification -- Version 2.0, Philips Semiconductor. 3. System Management Bus Specification -- Version 1.1, SBS Implementers Forum. 17.2. SMBus Configuration Figure 17.2 shows a typical SMBus configuration.
C8051F340/1/2/3/4/5/6/7 The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit.
C8051F340/1/2/3/4/5/6/7 17.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency. 17.3.3.
C8051F340/1/2/3/4/5/6/7 SMBus configuration options include: • • • • Timeout detection (SCL Low Timeout and/or Bus Free Timeout) SDA setup and hold time extensions Slave event enable/disable Clock source selection These options are selected in the SMB0CF register, as described in Section “17.4.1. SMBus Configuration Register” on page 198. Rev. 0.
C8051F340/1/2/3/4/5/6/7 17.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the INH bit.
C8051F340/1/2/3/4/5/6/7 Figure 17.4 shows the typical SCL generation described by Equation 17.2. Notice that THIGH is typically twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be extended low by slower slave devices, or driven low by contending master devices). The bit rate when operating as a master will never exceed the limits defined by equation Equation 17.1. Timer Source Overflows SCL TLow SCL High Timeout THigh Figure 17.4.
C8051F340/1/2/3/4/5/6/7 SFR Definition 17.1. SMB0CF: SMBus Clock/Configuration R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 R/W R/W R/W R/W R/W Reset Value EXTHOLD SMBTOE SMBFTE SMBCS1 SMBCS0 00000000 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC1 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly monitors the SDA and SCL pins. 0: SMBus interface disabled. 1: SMBus interface enabled. Bit6: INH: SMBus Slave Inhibit.
C8051F340/1/2/3/4/5/6/7 17.4.2. SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 17.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump to service routines. MASTER and TXMODE indicate the master/slave state and transmit/receive modes, respectively. STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus interrupt.
C8051F340/1/2/3/4/5/6/7 SFR Definition 17.2. SMB0CN: SMBus Control R R MASTER TXMODE Bit7 Bit6 R/W R/W STA STO Bit5 Bit4 R R ACKRQ ARBLOST Bit3 Bit2 R/W R/W Reset Value ACK SI 00000000 Bit1 Bit0 Bit Addressable SFR Address: 0xC0 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 202 MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: SMBus operating in Master Mode.
C8051F340/1/2/3/4/5/6/7 Table 17.3. Sources for Hardware Changes to SMB0CN Bit MASTER TXMODE STA STO ACKRQ ARBLOST ACK SI Set by Hardware When: • A START is generated. • START is generated. • SMB0DAT is written before the start of an SMBus frame. • A START followed by an address byte is received. • A STOP is detected while addressed as a slave. • Arbitration is lost due to a detected STOP. • A byte has been received and an ACK response value is needed.
C8051F340/1/2/3/4/5/6/7 17.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. Data in SMB0DAT is always shifted out MSB first.
C8051F340/1/2/3/4/5/6/7 S SLA W Interrupt A Data Byte Interrupt A Data Byte Interrupt A P Interrupt S = START P = STOP A = ACK W = WRITE SLA = Slave Address Received by SMBus Interface Transmitted by SMBus Interface Figure 17.5. Typical Master Transmitter Sequence Rev. 0.
C8051F340/1/2/3/4/5/6/7 17.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial data.
C8051F340/1/2/3/4/5/6/7 17.5.3. Slave Receiver Mode Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit (WRITE in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. Software responds to the received slave address with an ACK, or ignores the received slave address with a NACK.
C8051F340/1/2/3/4/5/6/7 17.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received. Upon entering Slave Transmitter Mode, an interrupt is generated and the ACKRQ bit is set.
C8051F340/1/2/3/4/5/6/7 Table 17.4. SMBus Status Decoding Values Written ARBLOST ACK 0 X A master START was generated. 0 0 0 1000 1 0 0 1 X 0 0 X 1 0 X 0 1 X Load next data byte into SMB0DAT. 0 0 X End transfer with STOP. 0 1 X End transfer with STOP and start another transfer. 1 1 X Send repeated START. 1 0 X Switch to Master Receiver Mode (clear SI without writing new data to SMB0DAT). 0 0 X Acknowledge received byte; Read SMB0DAT.
C8051F340/1/2/3/4/5/6/7 Table 17.4. SMBus Status Decoding (Continued) Values Written ACK STA STo ACK 0101 ARBLOST Status Vector 0100 ACKRQ Slave Transmitter Mode Values Read 0 0 0 A slave byte was transmitted; NACK received. No action required (expecting STOP condition). 0 0 X 0 0 1 A slave byte was transmitted; ACK received. Load SMB0DAT with next data byte to transmit. 0 0 X 0 1 X A Slave byte was transmitted; error detected.
C8051F340/1/2/3/4/5/6/7 18. UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “18.1. Enhanced Baud Rate Generation” on page 212). Received data buffering allows UART0 to start reception of a second incoming data byte before software has finished reading the previous data byte.
C8051F340/1/2/3/4/5/6/7 18.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 18.2), which is not user-accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1).
C8051F340/1/2/3/4/5/6/7 RS-232 LEVEL XLTR RS-232 TX C8051Fxxx RX OR TX TX RX RX MCU C8051Fxxx Figure 18.3. UART Interconnect Diagram 18.2.1. 8-Bit UART 8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
C8051F340/1/2/3/4/5/6/7 18.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit goes into RB80 (SCON0.
C8051F340/1/2/3/4/5/6/7 Master Device Slave Device Slave Device Slave Device V+ RX TX RX TX RX TX RX TX Figure 18.6. UART Multi-Processor Mode Interconnect Diagram Rev. 0.
C8051F340/1/2/3/4/5/6/7 SFR Definition 18.1. SCON0: Serial Port 0 Control R/W R R/W R/W R/W R/W R/W R/W Reset Value S0MODE - MCE0 REN0 TB80 RB80 TI0 RI0 01000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: 0x98 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 216 S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. UNUSED. Read = 1b.
C8051F340/1/2/3/4/5/6/7 SFR Definition 18.2. SBUF0: Serial (UART0) Port Data Buffer R/W R/W R/W R/W R/W R/W R/W R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value 00000000 SFR Address: 0x99 Bits7–0: SBUF0[7:0]: Serial Data Buffer Bits 7–0 (MSB-LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmission.
C8051F340/1/2/3/4/5/6/7 Table 18.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator SYSCLK = 48 MHz SYSCLK = 24 MHz SYSCLK = 12 MHz Target Baud Actual Baud Rate Error Baud Rate (bps) Rate (bps) 230400 230769 0.16% 115200 115385 0.16% 57600 57692 0.16% 28800 28846 0.16% 14400 14423 0.16% 9600 9615 0.16% 2400 2404 0.16% 1200 1202 0.16% 230400 230769 0.16% 115200 115385 0.16% 57600 57692 0.16% 28800 28846 0.16% 14400 14423 0.16% 9600 9615 0.16% 2400 2404 0.16% 1200 1202 0.
C8051F340/1/2/3/4/5/6/7 19. UART1 (C8051F340/1/4/5 Only) UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated baud rate generator with a 16-bit timer and selectable prescaler is included, which can generate a wide range of baud rates (details in Section “19.1. Baud Rate Generator” on page 220). A received data FIFO allows UART1 to receive up to three data bytes before data is lost and an overflow occurs. UART1 has six associated SFRs.
C8051F340/1/2/3/4/5/6/7 19.1. Baud Rate Generator The UART1 baud rate is generated by a dedicated 16-bit timer which runs from the controller’s core clock (SYSCLK), and has prescaler options of 1, 4, 12, or 48. The timer and prescaler options combined allow for a wide selection of baud rates over many SYSCLK frequencies. The baud rate generator is configured using three registers: SBCON1, SBRLH1, and SBRLL1. The UART1 Baud Rate Generator Control Register (SBCON1, SFR Definition 19.
C8051F340/1/2/3/4/5/6/7 19.2. Data Format UART1 has a number of available options for data formatting. Data transfers begin with a start bit (logic low), followed by the data bits (sent LSB-first), a parity or extra bit (if selected), and end with one or two stop bits (logic high). The data length is variable between 5 and 8 bits. A parity bit can be appended to the data, and automatically generated and detected by hardware for even, odd, mark, or space parity.
C8051F340/1/2/3/4/5/6/7 19.3. Configuration and Operation UART1 provides standard asynchronous, full duplex communication. It can operate in a point-to-point serial communications application, or as a node on a multi-processor serial interface. To operate in a point-to-point application, where there are only two devices on the serial bus, the MCE1 bit in SMOD1 should be cleared to ‘0’. For operation as part of a multi-processor communications bus, the MCE1 and XBE1 bits should both be set to ‘1’.
C8051F340/1/2/3/4/5/6/7 byte in the FIFO. After SBUF1 is read, the next byte in the FIFO is loaded into SBUF1, and space is made available in the FIFO for another incoming byte. If enabled, an interrupt will occur when RI1 is set. If the extra bit function is enabled (XBE1 = ‘1’) and the parity function is disabled (PE1 = ‘0’), the extra bit for the oldest byte in the FIFO can be read from the RBX1 bit (SCON1.2).
C8051F340/1/2/3/4/5/6/7 SFR Definition 19.1. SCON1: UART1 Control R/W R/W R R/W R/W R/W R/W R/W Reset Value OVR1 PERR1 THRE1 REN1 TBX1 RBX1 TI1 RI1 00100000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: 0xD2 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 224 OVR1: Receive FIFO Overrun Flag. This bit is used to indicate a receive FIFO overrun condition. 0: Receive FIFO Overrun has not occurred.
C8051F340/1/2/3/4/5/6/7 SFR Definition 19.2. SMOD1: UART1 Mode R/W R/W R/W R/W R/W R/W R/W R/W Reset Value MCE1 S1PT1 S1PT0 PE1 S1DL1 S1DL0 XBE1 SBL1 00001100 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address: 0xE5 Bit7: MCE1: Multiprocessor Communication Enable. 0: RI will be activated if stop bit(s) are ‘1’. 1: RI will be activated if stop bit(s) and extra bit are ‘1’ (extra bit must be enabled using XBE1).
C8051F340/1/2/3/4/5/6/7 SFR Definition 19.3. SBUF1: UART1 Data Buffer R/W R/W R/W R/W R/W R/W R/W R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value 00000000 SFR Address: 0xD3 Bits7–0: SBUF1[7:0]: Serial Data Buffer Bits 7–0 (MSB-LSB) This SFR is used to both send data from the UART and to read received data from the UART1 receive FIFO. Write: Writing a byte to SBUF1 initiates the transmission.
C8051F340/1/2/3/4/5/6/7 SFR Definition 19.5. SBRLH1: UART1 Baud Rate Generator High Byte R/W R/W R/W R/W R/W R/W R/W R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value 00000000 SFR Address: 0xB5 Bits7–0: SBRLH1[7:0]: High Byte of reload value for UART1 Baud Rate Generator. SFR Definition 19.6.
C8051F340/1/2/3/4/5/6/7 NOTES: 228 Rev. 0.
C8051F340/1/2/3/4/5/6/7 20. Enhanced Serial Peripheral Interface (SPI0) The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus.
C8051F340/1/2/3/4/5/6/7 20.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 20.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit first.
C8051F340/1/2/3/4/5/6/7 20.2. SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins.
C8051F340/1/2/3/4/5/6/7 Master Device 1 NSS GPIO MISO MISO MOSI MOSI SCK SCK GPIO NSS Master Device 2 Figure 20.2. Multiple-Master Mode Connection Diagram Master Device MISO MISO MOSI MOSI SCK SCK Slave Device Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram Master Device GPIO MISO MISO MOSI MOSI SCK SCK NSS NSS MISO MOSI Slave Device Slave Device SCK NSS Figure 20.4. 4-Wire Single Master Mode and Slave Mode Connection Diagram 232 Rev. 0.
C8051F340/1/2/3/4/5/6/7 20.3. SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift register, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer.
C8051F340/1/2/3/4/5/6/7 20.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0 should be disabled (by clearing the SPIEN bit, SPI0CN.
C8051F340/1/2/3/4/5/6/7 SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=1, CKPHA=0) MOSI MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NSS (4-Wire Mode) Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=1) MOSI MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 MISO MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 0 NSS (4-Wire Mode) Figure 20.7.
C8051F340/1/2/3/4/5/6/7 20.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following figures. SFR Definition 20.1.
C8051F340/1/2/3/4/5/6/7 SFR Definition 20.2. SPI0CN: SPI0 Control R/W R/W R/W SPIF WCOL MODF Bit7 Bit6 Bit5 R/W R/W R/W RXOVRN NSSMD1 NSSMD0 Bit4 Bit3 Bit2 R R/W Reset Value TXBMT SPIEN 00000110 Bit1 Bit Addressable SFR Address: 0xF8 Bit0 Bit 7: SPIF: SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service routine.
C8051F340/1/2/3/4/5/6/7 SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate R/W R/W R/W R/W R/W R/W R/W R/W Reset Value SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA2 Bits 7–0: SCR7–SCR0: SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation.
C8051F340/1/2/3/4/5/6/7 SCK* T T MCKH MCKL T T MIS MIH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 20.8. SPI Master Timing (CKPHA = 0) SCK* T T MCKH MCKL T T MIS MIH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 20.9. SPI Master Timing (CKPHA = 1) Rev. 0.
C8051F340/1/2/3/4/5/6/7 NSS T T SE T CKL SD SCK* T CKH T SIS T SIH MOSI T T SEZ T SOH SDZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 20.10. SPI Slave Timing (CKPHA = 0) NSS T T SE T CKL SD SCK* T CKH T SIS T SIH MOSI T SEZ T T SOH SLH MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 20.11. SPI Slave Timing (CKPHA = 1) 240 Rev. 0.
C8051F340/1/2/3/4/5/6/7 Table 20.1. SPI Slave Timing Parameters Parameter Description Min Max Units Master Mode Timing* (See Figure 20.8 and Figure 20.9) TMCKH SCK High Time 1 x TSYSCLK ns TMCKL SCK Low Time 1 x TSYSCLK ns 1 x TSYSCLK + 20 ns 0 ns TMIS MISO Valid to SCK Shift Edge TMIH SCK Shift Edge to MISO Change Slave Mode Timing* (See Figure 20.10 and Figure 20.
C8051F340/1/2/3/4/5/6/7 NOTES: 242 Rev. 0.
C8051F340/1/2/3/4/5/6/7 21. Timers Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, USB (frame measurements), Low-Frequency Oscillator (period measurements), or for general purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests.
C8051F340/1/2/3/4/5/6/7 The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section “15.1. Priority Crossbar Decoder” on page 149 for information on selecting and configuring external I/O pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is clocked by the system clock.
C8051F340/1/2/3/4/5/6/7 21.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set.
C8051F340/1/2/3/4/5/6/7 21.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/ timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock or prescaled clock.
C8051F340/1/2/3/4/5/6/7 SFR Definition 21.1. TCON: Timer Control R/W R/W R/W R/W R/W R/W R/W R/W TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: Reset Value 0x88 TF1: Timer 1 Overflow Flag. Set by hardware when Timer 1 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine.
C8051F340/1/2/3/4/5/6/7 SFR Definition 21.2. TMOD: Timer Mode R/W R/W R/W R/W R/W R/W R/W R/W Reset Value GATE1 C/T1 T1M1 T1M0 GATE0 C/T0 T0M1 T0M0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x89 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only when TR1 = 1 AND /INT1 is active as defined by bit IN1PL in register INT01CF (see SFR Definition 9.13). Bit6: C/T1: Counter/Timer 1 Select.
C8051F340/1/2/3/4/5/6/7 SFR Definition 21.3. CKCON: Clock Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value T3MH T3ML T2MH T2ML T1M T0M SCA1 SCA0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x8E Bit7: T3MH: Timer 3 High Byte Clock Select. This bit selects the clock supplied to the Timer 3 high byte if Timer 3 is configured in split 8-bit timer mode. T3MH is ignored if Timer 3 is in any other mode.
C8051F340/1/2/3/4/5/6/7 SFR Definition 21.4. TL0: Timer 0 Low Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x8A Bits 7–0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. SFR Definition 21.5. TL1: Timer 1 Low Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 00000000 0x8B Bits 7–0: TL1: Timer 1 Low Byte.
C8051F340/1/2/3/4/5/6/7 21.2. Timer 2 Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, USB Start-of-Frame (SOF) capture mode, or Low-Frequency Oscillator (LFO) Falling Edge capture mode. The Timer 2 operation mode is defined by the T2SPLIT (TMR2CN.3), T2CE (TMR2CN.4) bits, and T2CSS (TMR2CN.1) bits.
C8051F340/1/2/3/4/5/6/7 21.2.2. 8-bit Timers with Auto-Reload When T2SPLIT = ‘1’ and T2CE = ‘0’, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers operate in auto-reload mode as shown in Figure 21.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is always running when configured for 8-bit Mode.
C8051F340/1/2/3/4/5/6/7 21.2.3. Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge When T2CE = ‘1’, Timer 2 will operate in one of two special capture modes. The capture event can be selected between a USB Start-of-Frame (SOF) capture, and a Low-Frequency Oscillator (LFO) Falling Edge capture, using the T2CSS bit. The USB SOF capture mode can be used to calibrate the system clock or external oscillator against the known USB host SOF clock.
C8051F340/1/2/3/4/5/6/7 When T2SPLIT = ‘1’, the Timer 2 registers (TMR2H and TMR2L) act as two 8-bit counters. Each counter counts up independently and overflows from 0xFF to 0x00. Each time a capture event is received, the contents of the Timer 2 registers are latched into the Timer 2 Reload registers (TMR2RLH and TMR2RLL). A Timer 2 interrupt is generated if enabled.
C8051F340/1/2/3/4/5/6/7 SFR Definition 21.8. TMR2CN: Timer 2 Control R/W R/W R/W R/W R/W R/W R/W R/W Reset Value TF2H TF2L TF2LEN T2CE T2SPLIT TR2 T2CSS T2XCLK 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 0xC8 TF2H: Timer 2 High Byte Overflow Flag. Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00.
C8051F340/1/2/3/4/5/6/7 SFR Definition 21.9. TMR2RLL: Timer 2 Reload Register Low Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xCA Bits 7–0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2 when operating in auto-reload mode, or the captured value of the TMR2L register in capture mode. SFR Definition 21.10.
C8051F340/1/2/3/4/5/6/7 21.3. Timer 3 Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, USB Start-of-Frame (SOF) capture mode, or Low-Frequency Oscillator (LFO) Rising Edge capture mode. The Timer 3 operation mode is defined by the T3SPLIT (TMR3CN.3), T3CE (TMR3CN.4) bits, and T3CSS (TMR3CN.1) bits.
C8051F340/1/2/3/4/5/6/7 21.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is ‘1’ and T3CE = ‘0’, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers operate in auto-reload mode as shown in Figure 21.5. TMR3RLL holds the reload value for TMR3L; TMR3RLH holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is always running when configured for 8-bit Mode.
C8051F340/1/2/3/4/5/6/7 21.3.3. USB Start-of-Frame Capture When T3CE = ‘1’, Timer 3 will operate in one of two special capture modes. The capture event can be selected between a USB Start-of-Frame (SOF) capture, and a Low-Frequency Oscillator (LFO) Rising Edge capture, using the T3CSS bit. The USB SOF capture mode can be used to calibrate the system clock or external oscillator against the known USB host SOF clock.
C8051F340/1/2/3/4/5/6/7 When T3SPLIT = ‘1’, the Timer 3 registers (TMR3H and TMR3L) act as two 8-bit counters. Each counter counts up independently and overflows from 0xFF to 0x00. Each time a capture event is received, the contents of the Timer 3 registers are latched into the Timer 3 Reload registers (TMR3RLH and TMR3RLL). A Timer 3 interrupt is generated if enabled.
C8051F340/1/2/3/4/5/6/7 SFR Definition 21.13. TMR3CN: Timer 3 Control R/W R/W R/W R/W R/W R/W R/W TF3H TF3L TF3LEN T3CE T3SPLIT TR3 T3CSS Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 R/W Reset Value T3XCLK 00000000 Bit0 SFR Address: 0x91 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: TF3H: Timer 3 High Byte Overflow Flag. Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000.
C8051F340/1/2/3/4/5/6/7 SFR Definition 21.14. TMR3RLL: Timer 3 Reload Register Low Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x92 Bits 7–0: TMR3RLL: Timer 3 Reload Register Low Byte. TMR3RLL holds the low byte of the reload value for Timer 3 when operating in auto-reload mode, or the captured value of the TMR3L register when operating in capture mode. SFR Definition 21.15.
C8051F340/1/2/3/4/5/6/7 22. Programmable Counter Array (PCA0) The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and five 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line (CEXn) which is routed through the Crossbar to Port I/O when enabled (See Section “15.1.
C8051F340/1/2/3/4/5/6/7 22.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register. Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
C8051F340/1/2/3/4/5/6/7 22.2. Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: Edge-triggered Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP-51 system controller. These registers are used to exchange data with a module and configure the module's mode of operation. Table 22.
C8051F340/1/2/3/4/5/6/7 22.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/ timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn).
C8051F340/1/2/3/4/5/6/7 22.2.2. Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software.
C8051F340/1/2/3/4/5/6/7 22.2.3. High Speed Output Mode In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-Speed Output mode. Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/ Compare registers, the low byte should always be written first.
C8051F340/1/2/3/4/5/6/7 22.2.4. Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the output is toggled. The frequency of the square wave is then defined by Equation 22.1. F PCA F CEXn = ----------------------------------------2 × PCA0CPHn Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation. Equation 22.1.
C8051F340/1/2/3/4/5/6/7 22.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate a pulse width modulated (PWM) output on its associated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the value in PCA0CPLn, the output on the CEXn pin will be set.
C8051F340/1/2/3/4/5/6/7 22.2.6. 16-Bit Pulse Width Modulator Mode A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare module defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the output on CEXn is asserted high; when the counter overflows, CEXn is asserted low. To output a varying duty cycle, new value writes should be synchronized with PCA CCFn match interrupts.
C8051F340/1/2/3/4/5/6/7 22.3. Watchdog Timer Mode A programmable watchdog timer (WDT) function is available through the PCA Module 4. The WDT is used to generate a reset if the time between writes to the WDT update register (PCA0CPH4) exceed a specified limit. The WDT can be configured and enabled/disabled as needed by software. With the WDTE and/or WDLCK bits set to ‘1’ in the PCA0MD register, Module 4 operates as a watchdog timer (WDT).
C8051F340/1/2/3/4/5/6/7 Offset = ( 256 × PCA0CPL4 ) + ( 256 – PCA0L ) Equation 22.4. Watchdog Timer Offset in PCA Clocks The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH4 and PCA0H. Software may force a WDT reset by writing a ‘1’ to the CCF4 flag (PCA0CN.4) while the WDT is enabled. 22.3.2. Watchdog Timer Usage To configure the WDT, perform the following tasks: 1. Disable the WDT by writing a ‘0’ to the WDTE bit. 2.
C8051F340/1/2/3/4/5/6/7 22.4. Register Descriptions for PCA Following are detailed descriptions of the special function registers related to the operation of the PCA. SFR Definition 22.1. PCA0CN: PCA Control R/W R/W R/W R/W R/W R/W R/W R/W CF Bit7 CR - CCF4 CCF3 CCF2 CCF1 CCF0 00000000 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: (bit addressable) Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: 274 Reset Value 0xD8 CF: PCA Counter/Timer Overflow Flag.
C8051F340/1/2/3/4/5/6/7 SFR Definition 22.2. PCA0MD: PCA Mode R/W R/W R/W R/W R/W R/W R/W R/W CIDL WDTE Bit7 Bit6 Reset Value WDLCK - CPS2 CPS1 CPS0 ECF 01000000 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD9 Bit7: CIDL: PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle Mode. 0: PCA continues to function normally while the system controller is in Idle Mode. 1: PCA operation is suspended while the system controller is in Idle Mode.
C8051F340/1/2/3/4/5/6/7 SFR Definition 22.3.
C8051F340/1/2/3/4/5/6/7 SFR Definition 22.4. PCA0L: PCA Counter/Timer Low Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 00000000 0xF9 Bits 7–0: PCA0L: PCA Counter/Timer Low Byte. The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer. SFR Definition 22.5.
C8051F340/1/2/3/4/5/6/7 SFR Definition 22.7. PCA0CPHn: PCA Capture Module High Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xFC, 0xEA, 0xEC,0xEE, 0xFE PCA0CPHn Address: PCA0CPH0 = 0xFC (n = 0), PCA0CPH1 = 0xEA (n = 1), PCA0CPH2 = 0xEC (n = 2), PCA0CPH3 = 0xEE (n = 3), PCA0CPH4 = 0xFE (n = 4) Bits7–0: PCA0CPHn: PCA Capture Module High Byte. The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.
C8051F340/1/2/3/4/5/6/7 23. C2 Interface C8051F340/1/2/3/4/5/6/7 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash programming and in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2 protocol. 23.1.
C8051F340/1/2/3/4/5/6/7 C2 Register Definition 23.3. REVID: C2 Revision ID Reset Value Variable Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 This read-only register returns the 8-bit revision ID. C2 Register Definition 23.4. FPCTL: C2 Flash Programming Control Reset Value 00000000 Bit7 Bits7–0 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 FPCTL: Flash Programming Control Register. This register is used to enable Flash programming via the C2 interface.
C8051F340/1/2/3/4/5/6/7 23.2. C2 Pin Sharing The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and Flash programming functions may be performed. This is possible because C2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this halted state, the C2 interface can safely ‘borrow’ the C2CK (/RST) and C2D (P3.0) pins.
C8051F340/1/2/3/4/5/6/7 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: MCUinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.