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C8051T620/2-DK

C8051T620/2 DEVELOPMENT KIT USER’S GUIDE

1. Kit Contents

The C8051T620 and C8051T622 Development Kits contain the following items:

 C8051T62x Motherboard

 C8051T62x Emulation Daughter Board with C8051F34A installed

 Socket Daughter Board (one of the following):

C8051T62x QFN 32-pin (C8051T620DK)

C8051T622 QFN 24-pin (C8051T622DK)

 Twenty device samples (one of the following):

C8051T620-GM (C8051T620DK)

C8051T622-GM (C8051T622DK)

 C8051Txxx Development Kit Quick-Start Guide

 Product information CD-ROM includes:

Silicon Laboratories Integrated Development Environment (IDE)

Evaluation version of 8051 development tools (macro assembler, linker, C compiler)

Source code examples and register definition files

Documentation

 AC-to-DC universal power adapter

 Two USB cables

2. About the Daughter Boards

The C8051T620 and C8051T622 Development Kits include an Emulation Daughter Board (EDB) and a QFN

Socket Daughter Board (QFN-DB). The EDB has an installed C8051F34A device, which is a Flash-based device

that can be used for the majority of C8051T62x/32x code development. The QFN-DB is intended to allow both

programming and system-level debugging of C8051T62x/32x devices directly.

A C8051T62x/32x device cannot be erased once it has been programmed; so, it is advisable to use the

C8051F34A for the majority of code development. Refer to “AN368: Differences between the C8051F34A and the

C8051T62x and C8051T32x Device Families” for more details on how the C8051F34A can be used to develop

code for the C8051T62x/32x device families.

Summary of content (28 pages)

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C8 0 5 1 T6 2 0 / 2 - DK C8051T620/2 D E V E L O P M E N T K I T U SER ’ S G UIDE 1.
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C8051T620/2-DK 3. Hardware Setup See Figure 1 for a diagram of the hardware configuration. 1. 2. 3. 4. Attach the desired daughter board to the motherboard at connectors P1 and P2. If using the QFN Socket Daughter Board, place the device to be programmed into the socket. Place shorting blocks on J7 and the +3VD-VDD_PWR jumper pair on J6, as shown in Figure 1. Connect the motherboard’s P5 USB connector to a PC running the Silicon Laboratories IDE using the USB Cable. 5.
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C8051T620/2-DK 4. Software Installation The included CD-ROM contains the Silicon Laboratories Integrated Development Environment (IDE), 8051 evaluation toolset, Virtual COM Port drivers for the CP210x USB to UART Bridge, and additional documentation. Insert the CD-ROM into your PC's CD-ROM drive. An installer will automatically launch, allowing you to install the IDE software or read documentation by clicking buttons on the installation panel.
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C8051T620/2-DK 5. Software Overview The following software is necessary to build a project, download code to, and communicate with the target microcontroller.   8051 Evaluation Toolset Silicon Labs Integrated Development Environment (IDE) Other useful software that is provided on the development kit CD and the Silicon Labs Downloads website ( www.silabs.
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C8051T620/2-DK 6. Click the Connect button in the toolbar or select DebugConnect from the menu to connect to the device. 7. Download the project to the target by clicking the Download Code button in the toolbar. Note: To enable automatic downloading if the program build is successful, select Enable Automatic Connect/Download after Build in the ProjectTarget Build Configuration dialog. If errors occur during the build process, the IDE will not attempt the download. 8.
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C8051T620/2-DK The Configuration Wizard utility helps accelerate development by automatically generating initialization source code to configure and enable the on-chip resources needed by most design projects. In just a few steps, the wizard creates complete startup code for a specific Silicon Laboratories MCU. The program is configurable to provide the output in C or assembly language.
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C8051T620/2-DK 6. Example Source Code Example source code and register definition files are provided by default in the SiLabs\MCU\Examples\C8051T620_1_T320_3 or SiLabs\MCU\Examples\C8051T622_3_T326_7 directory during IDE installation. These files may be used as a template for code development. 6.1. Register Definition Files Register definition files C8051T620.inc, C8051T622.inc, C8051T620_defs.h, C8051T622_defs.h, and compiler_defs.h define all SFR registers and bit-addressable control/status bits.
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C8051T620/2-DK 7. Development Boards The C8051T620/2 Development Kit includes a motherboard that interfaces to various daughter boards. The C8051T62x Emulation Daughter Board contains a C8051F34A device to be used for preliminary software development. The C8051T620 Socket Daughter Board and C8051T622 Socket Daughter Board allow programming and evaluation of the actual C8051T62x devices. Numerous input/output (I/O) connections are provided on the motherboard to facilitate prototyping.
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C8051T620/2-DK SW1 J1 J14 C8051T62x-MB P1 LED1 LED2 SW2 P0.1 P1.2 SW1 LED2 P2.0 P2.3 P1.0 SW2 P2.1 SILICON LABS www.silabs.com P0.6 LED1 P2.2 J9 J2 P3 J10 J15 VPP J7 J3 PWR J6 J4 D10 USB P2ACTIVE D11 USB ACTIVE CP2103 DEBUG PWR U1 J8 RTS_DEBUG P1.1 RTS_COMM D12 STOP RUN J5 U2 VDD_PWR VDD_PWR VDD_PWR VDD_PWR +3VD VDD_EXT VDD_DEBUG VDD_COMM F326 CTS_DEBUG P1.2 CTS_COMM J12 J13 P5 J11 RX_DEBUG P0.4 RX_COMM P4 TX_DEBUG P0.5 TX_COMM RESET R8 Figure 3.
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C8051T620/2-DK C8051T62x EDB P3 U1 F34A VBUS VDD SILICON LABS www.silabs.com VREGIN VREGIN Figure 5. C8051T62x Emulation Daughter Board C8051T62x QFN32 SKT DB J3 VBUS VREGIN SILICON LABS www.silabs.com J1 VDD VREGIN P3 VDD VIO J2 Figure 6. C8051T620 QFN32 Socket Daughter Board C8051T622 QFN24 SKT DB J3 SILICON LABS VBUS VREGIN www.silabs.com J1 VDD VREGIN P3 VDD VIO J2 Figure 7. C8051T622 QFN24 Socket Daughter Board 10 Rev. 0.
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C8051T620/2-DK C8051T320 QFP32 SKT DB SILICON LABS J2 VBUS VREGIN www.silabs.com P3 VDD VREGIN J1 Figure 8. C8051T320 QFP32 Socket Daughter Board C8051T321 QFN28 SKT DB SILICON LABS www.silabs.com VBUS VREGIN J2 P3 VDD VREGIN J1 Figure 9. C8051T321 QFN28 Socket Daughter Board C8051T326 QFN28 SKT DB J3 SILICON LABS VBUS VREGIN www.silabs.com J1 VDD VREGIN P3 VDD VIO J2 Figure 10. C8051T326 QFN28 Socket Daughter Board Rev. 0.
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C8051T620/2-DK C8051T327 QFN28 SKT DB J3 SILICON LABS VBUS VREGIN www.silabs.com J1 VDD VREGIN P3 Figure 11. C8051T327 QFN28 Socket Daughter Board 12 Rev. 0.
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C8051T620/2-DK 7.1. System Clock Sources The C8051T62x/32x devices feature a calibrated internal oscillator that is enabled as the system clock source on reset. After reset, the internal oscillator operates at a frequency of 48 MHz (±1.5%) by default but may be configured by software to operate at other frequencies. Therefore, in many applications, an external oscillator is not required.
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C8051T620/2-DK Table 2 lists the port pins and headers corresponding to the switches, LEDs, and potentiometer. Table 2. Motherboard I/O Descriptions Description Component Name I/O Header Switch SW1 Daughter Card's P0.1 Daughter Card’s P2.0 J9 [2-4] J9 [4-6] Switch SW2 Daughter Card’s P1.0 Daughter Card’s P2.1 J9 [1-3] J9 [3-5] RESET SW3 Daughter Card's RST/C2CK None Green LED labeled “LED1” D1 Daughter Card's P0.6 Daughter Card's P2.
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C8051T620/2-DK 7.4. USB Debug Adapter (DEBUG/P5) A Universal Serial Bus (USB) connector (P5) provides the onboard debug and programming interface. The debug/ programming MCU and associated circuitry are powered through the USB connector, which can also supply the rest of the motherboard by routing the USB Debug Adapter's power through J6. The USB Debug Adapter also provides a data communications interface that can be used when the debug adapter is not debugging or programming a C8051T62x/32x device. 7.5.
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C8051T620/2-DK 7.8. Analog I/O (J1 and J14) Three of the C8051T62x/32x target device's port pins are connected to the J1 terminal block. The terminal block also allows users to input an external voltage that can be used as the power supply of the board. Refer to Table 3 for the J1 terminal block connections. Placing a shorting block on J14 will connect the P0.7/VREF signal on J1 to the P0.7 pin of the device. Table 3. J1 Terminal Block Descriptions Pin # Description 1 VREGIN 2 VIO 3 GND 4 P2.
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C8051T620/2-DK 7.10. Using Alternate Supplies with the C8051T62x Development Kit For most evaluation purposes, the onboard 3.3 V supply regulator is sufficient to be used as a VDD power supply. However, in applications where a different supply voltage is desired (e.g., 1.8 V), an external supply voltage can be applied to the board at the analog connector (J1). Some devices in the C8051T62x/32x family also support a separate voltage input for the input/output voltage of the port pins.
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Figure 14. C8051T62x Motherboard Schematic (1 of 2) C8051T620/2-DK 8. Schematics 18 Rev. 0.
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Figure 15. C8051T62x Motherboard Schematic (2 of 2) C8051T620/2-DK Rev. 0.
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Figure 16. C8051T62x Emulation Daughter Board Schematic C8051T620/2-DK 20 Rev. 0.
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Figure 17. C8051T620 QFN-32 Daughter Board Schematic C8051T620/2-DK Rev. 0.
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Figure 18. C8051T622 QFN-24 Daughter Board Schematic C8051T620/2-DK 22 Rev. 0.
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Figure 19. C8051T320 QFP-32 Daughter Board Schematic C8051T620/2-DK Rev. 0.
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Figure 20. C8051T321 QFN-28 Daughter Board Schematic C8051T620/2-DK 24 Rev. 0.
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Figure 21. C8051T326 QFN-28 Daughter Board Schematic C8051T620/2-DK Rev. 0.
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Figure 22. C8051T327 QFN-28 Daughter Board Schematic C8051T620/2-DK 26 Rev. 0.
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C8051T620/2-DK DOCUMENT CHANGE LIST Revision 0.2 to Revision 0.3      Updated "4.2. Development Tools Installation" on page 3. Updated "4.3. CP210x USB to UART VCP Driver Installation" on page 3. Updated Figure 17 on page 21. Updated Figure 18 on page 22. Updated Figure on page 27. Revision 0.3 to Revision 0.4  Updated "1. Kit Contents" on page 1. Updated "2. About the Daughter Boards" on page 1.  Updated "6. Example Source Code" on page 7.  Updated project paths  Updated "7.
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C8051T620/2-DK CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.