Specifications

AN93
Rev. 0.8 147
To prevent polarity reversals from being detected as a
loss of loop current, a debounce timer controlled by U-
registers 50 and 51 is used. However, if the HOI bit is
set, a parallel phone intrusion while off-hook will give a
“LINE IN USE” result code to indicate that the Si2493/
57/34/15/04 has gone on-hook due to a parallel phone
intrusion.
Intrusion Detection—Off-Hook Condition
When the ISOmodem is off-hook, the U79[4:0] (LVCS)
value represents loop current. Additionally, the
ISOmodem is typically in the data mode, and it is
difficult for the host to monitor the LVCS value. For this
reason, a controller-based off-hook intrusion algorithm
is used.
There is a delay between the ISOmodem going off-hook
and the start of the intrusion algorithm set by
U77[15:12] (IST) (Intrusion Settling Time). This avoids
false intrusion detection due to loop transients during
the on-hook to off-hook transition. The off-hook intrusion
algorithm monitors the value of LVCS at a sample rate
determined by U76[15:9] (OHSR). The algorithm
compares each LVCS sample to the reference value in
U76[4:0] (ACL). ACL = 0 at the first off-hook event after
reset unless a value is written to it by the host. If
ACL = 0, the ISOmodem does not begin the intrusion
algorithm until after two LVCS samples have been
received. If the host writes a non-zero value to ACL
prior to the ISOmodem going off-hook, a parallel phone
intrusion occurring during the IST interval and
maintained until the end of the IST interval triggers a
PPD interrupt. The ISOmodem also automatically
updates ACL with the LVCS value while off-hook if an
intrusion has not occurred. An ACL value can be written
by the host and forced to remain unchanged by setting
U76[8] (FACL) = 1b. If LVCS is lower than ACL by an
amount greater than the value set in U76[7:5] (DCL)
(6 mA default) for two consecutive samples,
U70[2] (PPD), Parallel Phone Detect is set. If
U70[10] (PPDM) (Parallel Phone Detect Mask) is set to
1b (default condition), the INT
pin (Si2493/57/34/15/04,
pin 14) in serial mode or the INT bit (Parallel Interface
Register 1, bit 3) in parallel mode is also triggered. The
host can monitor PPD or issue an AT:I to verify the
cause of an interrupt and clear PPD. The host can take
the appropriate action when the intrusion is confirmed.
The Intrusion Detection Algorithm is as follows:
if LVCS(t) = LVCS (t – 40 ms x OHSR)
and ACL – LVCS(t) < DCL
then ACL = LVCS(t)
if (ACL – LVCS (t – 40 ms x OHSR) > DCL
and ACL – LVCS(t) > DCL
then PPD = 1
and INT
(or INT bit in parallel mode) is asserted
(PPDM = 1)
The ISOmodem can also be programmed to go on-hook
automatically on a PPD interrupt by setting
U77 (HOI)[11] (Hang-Up On Intrusion) to 1b.
The off-hook intrusion algorithm may be suspended for
a period defined by U78[15:14] (IB) after the start of
dialing. This guards against false PPD detects due to
dial pulses or other transients caused by Central Office
switching.
Table 97 lists the U-Registers and bits used for Intrusion
Detection.
The Si2493/57/34/15/04 has an internal analog-to-
digital converter used to monitor the loop voltage when
on-hook and loop current when off-hook to check for
parallel devices going off-hook. The host measures loop
voltage or current by reading U79[4:0] (LVCS). To set
the Si2493/57/34/15/04 to monitor loop voltage in the
on-hook state, the host issues the following commands:
Table 97. Intrusion Detection
Register Bit(s) Name Function
U70 10 PPDM Parallel Phone Detect
Mask
U70 2 PPD Parallel Phone Detect
U76 15:9 OHSR Off-Hook Sample Rate
U76 8 FACL Force ACL
U76 7:5 DCL Differential Current
Level
U76 4:0 ACL Absolute Current Level
U77 15:12 IST Intrusion Settling Time
U77 11 HOI Hang-Up On Intrusion
U78 15:14 IB Intrusion Blocking
U78 7:0 IS Intrusion Suspend
U79 4:0 LVCS Line Voltage/Current
Sense
U83 15:0 NOLN No Line Threshold %V1
U84 15:0 LIUS Line-in-use Threshold
%V1
U85 15:0 NLIU Line-in-use/No Line
Threshold %V2