Specifications

AN93
72 Rev. 0.9
U4E 0x004E PRDD Pre-dial delay-time—(ms units). 0x0000
U4F 0x004F FHT Flash hook time—(ms units). 0x01F4
U50 0x0050 LCDN Loop current debounce on time (ms units). 0x015E
U51 0x0051 LCDF Loop current debounce off time (ms units). 0x00C8
U52 0x0052 XMTL Transmit level adjust (1 dB units) 0x0000
U53 0x0053 MOD2 This is a bit-mapped register. 0x0000
U62 0x0062 DAAC1 This is a bit-mapped register. 0x0804
U63 0x0063 DAAC3 This is a bit-mapped register. 0x0003
U65 0x0065 DAAC4 This is a bit-mapped register. 0x00E0
U66 0x0066 DAAC5 This is a bit-mapped register. 0xXX40
U67 0x0067 ITC1 This is a bit-mapped register. 0x0008
U68 0x0068 ITC2 This is a bit-mapped register. 0x0000
U6A 0x006A ITC4 This is a bit-mapped register (read only). N/A
U6C 0x006C LVS This is a bit-mapped register. 0xXX00
U6E 0x006E CK1 This is a bit-mapped register. 0x7F20
U6F 0x006F PTME This is a bit-mapped register. 0x00FF
U70 0x0070 IO0 This is a bit-mapped register. 0x2700
U71 0x0071 IO1 This is a bit-mapped register. 0x0000
U76 0x0076 GEN1 This is a bit-mapped register. 0x3240
U77 0x0077 GEN2 This is a bit-mapped register. 0x401E
U78 0x0078 GEN3 This is a bit-mapped register. 0x0000
U79 0x0079 GEN4 This is a bit-mapped register. 0x00XX
U7A 0x007A GENA This is a bit-mapped register. 0x0000
U7C 0x007C GENC This is a bit-mapped register. 0x0000
U7D 0x007D GEND This is a bit-mapped register. 0x0000
U83 0x0083 NOLN No-Line threshold. If %V1 is set, NOLN sets the threshold for
determination of line present vs. line not present. 3 V/bit
0x0001
U84 0x0084 LIUS Line-in-use threshold. If %V1 is set, LIUS sets the threshold for
determination of line in use vs. line not in use. 3 V/bit
0x0007
U85 0x0085 NLIU Line-in-use/No line threshold. If %V2 is set, NLIU sets the thresh-
old reference for the adaptive algorithm (see %V2). 3 V/bit
0x0000
Table 32. U-Register Descriptions (Continued)
Register Address
(Hex)
Name Description Default
Value