User`s guide

Si47xx-EVB
12 Rev. 0.8
2.1.3. Reference Clock
Figure 6. Reference Clock Block Diagram
The Si47xx accepts a 32.768 kHz reference clock at the RCLK pin. On the EVB, this clock is provided by a
precision crystal oscillator. The user has the option of not using the onboard oscillator and bringing in the reference
clock from an external source through SMA connector J54.
When the user chooses to provide an external RCLK, jumper J52 has to be set accordingly. The user has the
option to turn off the onboard crystal oscillator by installing jumper J57.
2.1.4. Audio I/O
Figure 7. Audio I/O Block Diagram
Daughterboard
Si47xx
RCLK
9
X1
32.768 kHz
INT RClk
Jumper
J52
J54
EXT
RClk
Jumper
J57
DIS_INT_RCLK
INT_RCLK
EXT_RCLK
Note: Jumper J44 and J45 are automatically configured in EVB Rev 1.3.
Jumper
J5&J13
EVB In (TX only) 47xx Audio2 47xx Audio1 EVB Out (RX only)
1
0
0
1
CODEC OUT
DIN
LINE
OUT
CODEC IN
LINE
IN
DOUT
S/PDIF IN
SPDIF
IN
DOUT
S/PDIF OUT
DIN
SPDIF
OUT
0
1
0
1
Jumper
J45
TX: Analog/Digital In TX: Analog In TX: Digital In RX: Analog/Digital Out
RX: Digital Out RX: Analog Out
AUDIO2
To_TX
From_RX
AUDIO1
From_RX
To_TX
Jumper
J44
RCA In
Line In
(white)
SPDIF In
(white)
RCA Out
Line Out
(black)
SPDIF Out
(black)
Si47xx
(Daughterboard)
LIN/ DFS2
RIN/ DOUT
LOUT/ DFS1
ROUT/ DIN
14
13
AUDIO1
AUDIO2
15
16
J7
J19
J19
J6
J30
J30
Audio2
Select
Audio1
Select
Digital Input
Select