User guide

16 www.xilinx.com AC701 Evaluation Board
UG952 (v1.1) January 30, 2013
Chapter 1: AC701 Evaluation Board Features
The AC701 board DDR3 memory interface adheres to the constraints guidelines
documented in the DDR3 Design Guidelines section of
UG586, 7 Series FPGAs Memory
Interface Solutions User Guide. The AC701 board DDR3 memory interface is a 40Ω
impedance implementation. Other memory interface details are available in
UG586 and
UG473, 7 Series FPGAs Memory Resources User Guide.
Quad-SPI Flash Memory
[Figure 1-2, callout 3]
The Quad-SPI Flash memory U7 provides 256 Mb of non-volatile storage that can be used
for configuration and data storage.
• Part number: N25Q256A13ESF40G (Numonyx)
• Supply voltage: 3.3V
• Data path width: 4 bits
• Data rate: Various depending on Single/Dual/Quad mode and CCLK rate
Four data lines and the FPGA's CCLK pin are wired to the Quad-SPI Flash memory. The
connections between the SPI Flash memory and the FPGA are listed in
Table 1-5.
The configuration section of UG470, 7 Series FPGAs Configuration User Guide provides details
on using the Quad-SPI Flash memory. Figure 1-5 shows the connections of the Quad-SPI
P1 DDR3_RAS_B 110 RAS_B
P4 DDR3_CKE0 73 CKE0
N4 DDR3_CKE1 74 CKE1
L2 DDR3_CLK0_N 103 CK0_N
M2 DDR3_CLK0_P 101 CK0_P
N2 DDR3_CLK1_N 104 CK1_N
N3 DDR3_CLK1_P 102 CK1_P
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
U1 FPGA Pin Net Name
J1 DDR3 Memory
Pin Number Pin Name
Table 1-5: Quad-SPI Flash Memory Connections to the FPGA
U1 FPGA Pin Net Name
U7 Quad-SPI Flash Memory
Pin Number Pin Name
R14 FLASH_D0 15 DQ0
R15 FLASH_D1 8 DQ1
P14 FLASH_D2 9 DQ2
N14 FLASH_D3 1 DQ3
H13 FPGA_CCLK 16 C
P18 QSPI_IC_CS_B 7 S_B