User guide

AC701 Evaluation Board www.xilinx.com 23
UG952 (v1.1) January 30, 2013
Feature Descriptions
Programmable User Clock Source
[Figure 1-2, callout 7]
The AC701 board has a programmable low-jitter 3.3V differential oscillator (U34) driving
the FPGA MRCC inputs of bank 14. This USER_CLOCK_P and USER_CLOCK_N clock
signal pair are connected to FPGA U1 pins M21 and M22 respectively. On power-up the
user clock defaults to an output frequency of 156.250
MHz. User applications can change
the output frequency within the range of 10
MHz to 810 MHz through an I
2
C interface.
Power cycling the AC701 board will revert the user clock to its default frequency of
156.250
MHz.
• Programmable Oscillator: Silicon Labs Si570BAB000544DG (10 MHz - 810 MHz)
• Differential Output
The user clock circuit is shown in Figure 1-11.
References
The Silicon Labs Si570 data sheet is available from http://www.silabs.com.
X-Ref Target - Figure 1-11
Figure 1-11: User Clock Source
UG952_c1_11_101512
GND
VCC3V3
Si570
Programmable
Oscillator
NC
OE
GND
SCL
SDA
VDD
1
2
3
8
7
6
U34
R15
4.7KΩ 5%
USER CLOCK N
C192
0.01 μF 25V
X7R
CLK-
4
5
GND
VCC3V3
CLK+
USER CLOCK P
USER CLOCK SDA
USER CLOCK SCL
10 MHz - 810 MHz
To
I
2
C
Bus Switch
(U49)