User guide

AC701 Evaluation Board www.xilinx.com 25
UG952 (v1.1) January 30, 2013
Feature Descriptions
GTP Clock MUX
The AC701 board FPGA U1 MGT Bank 213 has two clock inputs, MGTREFCLK0 and
MGTREFCLK1. Each clock input is driven by a capacitively-coupled clock sourced from a
SY9544UMG 4-to-1 MUX.
Each MUX has a clock source at three of its four inputs, the fourth input is not connected.
Clock MUX U3 SY89544UMG drives Bank 213 MGTREFCLK0 pins AA13 (P) and AB13
(N), and clock MUX U4 SY89544UMG drives Bank 213 MGTREFCLK1 pins AA11 (P) and
AB11 (N). See
Table 1-10 for clock MUX U3 connections, and Table 1-11 for clock MUX U4
connections.
Table 1-9 lists the MGT sources for U3 and U4.
Table 1-9: MGT Clock MUX U3 and U4 Clock Sources
Clock Name Reference Description
125 MHz Clock
Generator
U2
ICS844021 Crystal-to-LVDS Clock Generator (ICS).
See 125 MHz Clock Generator, page 26.
GTP SMA REF Clock
(differential pair)
J25
SMA_MGT_REFCLK_P (net name).
See GTP SMA Clock Input, page 26.
J26
SMA_MGT_REFCLK_N (net name).
See GTP SMA Clock Input, page 26.
Jitter Attenuated
Clock
U24
Si5324C LVDS precision clock multiplier/jitter
attenuator (Silicon Labs).
See Jitter Attenuated Clock, page 27.
FMC HPC GBT
Clocks
J30
FMC_HPC_GBTCLK0_M2C_C_P/N (net name) (U3),
FMC_HPC_GBTCLK1_M2C_C_P/N (net name) (U4).
See FMC HPC GBT Clocks, page 28.