User guide

26 www.xilinx.com AC701 Evaluation Board
UG952 (v1.1) January 30, 2013
Chapter 1: AC701 Evaluation Board Features
125 MHz Clock Generator
[Figure 1-2, callout 15]
Clock MUX U3 input 0 (pin4 P, pin 2 N) is driven by U2 ICS84402I Crystal-to-LVDS clock
generator. This device uses 25
MHz crystal X3 as its base input frequency and, via an
internal VCO, multiplies this by five to produce a 0.45
ps (typical) RMS phase jitter,
125
MHz LVDS output. The circuit for the 125 MHz clock is shown in Figure 1-13.
GTP SMA Clock Input
[Figure 1-2, callout 9]
The AC701 board includes a pair of SMA connectors for a GTP clock that are wired to GTP
quad bank 213 via clock MUX U4. This differential clock has signal names
SMA_MGT_REFCLK_P and SMA_REFCLK_N, which are connected to MGT clock MUX
U4 input 0 pins 4 and 2 respectively. The clock MUX output pins 10 (P-side) and 11 (N-side)
are capacitively coupled to FPGA U1 GTP quad 213 MGTREFCLK1 pin AA11 and AB11
respectively.
Figure 1-14 shows this direct-coupled SMA clock input circuit.
• External user-provided GTP reference clock on SMA input connectors
• Differential Input
X-Ref Target - Figure 1-13
Figure 1-13: AC701 Board 125 MHz U3 MUX Input0 Source Circuit
GND_EPHYCLK GND_EPHYCLKGND_EPHYCLK
R320
1.0M 5%
R487
0Ω 5%
R486
0Ω 5%
C300
18pF 50V
NPO
C301
18pF 50V
NPO
EPHYCLK_XTAL_OUT
GND2
GND1
X2
X1
X3
25.00 MHz
50 ppm
EPHYCLK_XTAL_IN
2
1
3
4
VDD
Q0
NQ0
OE
XTAL_OUT
XTAL_IN
GND
VDDA
8
7
6
5
3
4
2
1
U2
VDDA_EPHYCLK
EPHYCLK_Q0_C_N EPHYCLK_Q0_N
EPHYCLK_Q0_C_P EPHYCLK_Q0_P
ICS844021I
VDD_EPHYCLK
UG952_c1_13_101512
X-Ref Target - Figure 1-14
Figure 1-14: GTP SMA Clock Source
UG952_c1_14_101512
SMA_MGT_REFCLK_PSMA_MGT_REFCLK_C_P
SMA
Connector
J25
GND
R485
0Ω 5%
0Ω 5%
SMA_MGT_REFCLK_NSMA_MGT_REFCLK_C_N
SMA
Connector
J26
GND
R484