User guide

28 www.xilinx.com AC701 Evaluation Board
UG952 (v1.1) January 30, 2013
Chapter 1: AC701 Evaluation Board Features
FMC HPC GBT Clocks
The FMC HPC connector J30 sources two MGT clocks, FMC1_HPC_GBTCLK0_M2C_P/N
from connector section
D, and FMC1_HPC_GBTCLK1_M2C_P/N from connector
section
B. Table 1-10 and Table 1-11 list the MGT clock MUX U3 and U4 connections.
The MUX U3 clock input channel select nets are SFP_MGT_CLK_SEL[1:0].
SFP_MGT_CLK_SEL1 is wired to FPGA U1 pin C24 and SFP_MGT_CLK_SEL0 is wired to
FPGA U1 pin B26 on FPGA U1 Bank 16.
The MUX U4 clock input channel select nets are PCIE_MGT_CLK_SEL[1:0].
PCIE_MGT_CLK_SEL1 is wired to FPGA U1 pin C26 and PCIE_MGT_CLK_SEL0 is wired
to FPGA U1 pin A24 on FPGA U1 Bank 16.
The U3 MUX circuit is shown in Figure 1-16. The U4 MUX circuit is shown in Figure 1-17.
Table 1-10: MUX U3 SY89544UMG MGT Clock Inputs
Clock Source
Schematic Net Name
SY89544UMG U3
Schematic Net Name
FPGA U1 Bank 213
Device
Ref
Des
Pin Input Pin Output Pin Pin Pin Name
ICS84402I U2
7EPHYCLK_Q0_P
IN0
4
Qout_P 10
Qout_N 11
SFP_MGT_CLK0_P
(1)
SFP_MGT_CLK0_N
(1)
AA13
AB13
MGTREFCLK0P
MGTREFCLK0N
6EPHYCLK_Q0_N 2
SI5324-C-GM U24
29 SI5324_OUT0_C_N
IN1
32
28 SI5324_OUT0_C_P 30
FMC HPC J30
D4
FMC1_HPC_
GBTCLK0_M2C_P
IN2
27
D5
FMC1_HPC_
GBTCLK0_M2C_N
25
Notes:
1. U3 output clock nets SFP_MGT_CLK0_P/N contain a series 0.1uF capacitor.
Table 1-11: MUX U4 SY89544UMG MGT Clock Inputs
Clock Source
Schematic Net Name
SY89544UMG U4 Schematic Net Name FPGA U1 Bank 213
Device
Ref
Des
Pin Input Pin Output Pin Pin Pin Name
SMA J25 1 SMA_MGT_REFCLK_P
IN0
4
Qout_P 10
Qout_N 11
SFP_MGT_CLK1_P
(1)
SFP_MGT_CLK1_N
(1)
AA11
AB11
MGTREFCLK1P
MGTREFCLK1N
SMA J26 1 SMA_MGT_REFCLK_N 2
SI5324-C-GM U24
35 SI5324_OUT1_C_P
IN1
32
34 SI5324_OUT1_C_N 30
FMC HPC J30
B20
FMC1_HPC_
GBTCLK1_M2C_P
IN2
27
B21
FMC1_HPC_
GBTCLK1_M2C_N
25
Notes:
1. U4 output clock nets SFP_MGT_CLK1_P/N contain a series 0.1uF capacitor.