User guide

AC701 Evaluation Board www.xilinx.com 29
UG952 (v1.1) January 30, 2013
Feature Descriptions
X-Ref Target - Figure 1-16
Figure 1-16: MGT Clock MUX U3 Circuit
Q24
NDS336P
460 mW
SFP_MGT_CLK_SEL0
MGT_CLK0_SEL0
MGT_CLK0_SEL1
SFP_MGT_CLK0_P
SFP_MGT_CLK0_P
0
VCC1
VCC2
FMC1_HBC_GBTCLK0_M2C_C_P
IN0
Q
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
Q
GND1
GND2
GND3
GND4
GND5
GND6
PWRPAD
VT0
IN0
IN1
NC
NC
NC
NC
NC
NC
VT1
IN1
IN2
VT2
IN2
IN3
VT3
IN3
SEL0
SEL1
1
2
3
S0
S1
U3
SY89544UMG
50
50
50
50
50
50
50
50
VCC2V5
VCC2V5
FMC1_HBC_GBTCLK0_M2C_C_N
EPHYCLK_Q0_P
EPHYCLK_Q0_N
SI5324_OUT0_C_P
SI5324_OUT0_C_N
18
17
20
24
28
29
10
11
7
9
12
13
16
18
33
5
4
3
2
32
31
30
27
26
25
23
22
21
6
19
GND
GND
VCC2V5
Q25
NDS336P
460 mW
SFP_MGT_CLK_SEL1
GND
VCC2V5
R332
10K
1/10W
1%
R333
10K
1/10W
1%
R455
10K
1/10W
1%
R454
10K
1/10W
1%
C105
0.1μF
25V
X5R
C320
0.1μF
25V
X5R
C318
0.1μF
25V
X5R
GND
UG952_c1_16_101612
TO MGT BANK 213
MGTREFCLK0_P/N
PINS AA13, AB13