User guide

30 www.xilinx.com AC701 Evaluation Board
UG952 (v1.1) January 30, 2013
Chapter 1: AC701 Evaluation Board Features
X-Ref Target - Figure 1-17
Figure 1-17: MGT Clock MUX U4 Circuit
Q23
NDS336P
460 mW
PCIE_MGT_CLK_SEL0
MGT_CLK1_SEL0
MGT_CLK1_SEL1
SFP_MGT_CLK1_P
SFP_MGT_CLK1_P
0
VCC1
VCC2
FMC1_HBC_GBTCLK1_M2C_C_P
IN0
Q
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
Q
GND1
GND2
GND3
GND4
GND5
GND6
PWRPAD
VT0
IN0
IN1
NC
NC
NC
NC
NC
NC
VT1
IN1
IN2
VT2
IN2
IN3
VT3
IN3
SEL0
SEL1
1
2
3
S0
S1
U4
SY89544UMG
50
50
50
50
50
50
50
50
VCC2V5
VCC2V5
FMC1_HBC_GBTCLK1_M2C_C_N
SMA_MGT_REFCLK_P
SMA_MGT_REFCLK_N
SI5324_OUT1_C_P
SI5324_OUT1_C_N
18
17
20
24
28
29
10
11
7
9
12
13
16
18
33
5
4
3
2
32
31
30
27
26
25
23
22
21
6
19
GND
GND
VCC2V5
Q22
NDS336P
460 mW
PCIE_MGT_CLK_SEL1
GND
VCC2V5
R151
10K
1/10W
1%
R152
10K
1/10W
1%
R453
10K
1/10W
1%
R452
10K
1/10W
1%
C106
0.1μF
25V
X5R
TO MGT BANK 213
MGTREFCLK1_P/N
PINS AA11, AB11
C321
0.1μF
25V
X5R
C322
0.1μF
25V
X5R
GND
UG952_c1_17_101612