User guide

AC701 Evaluation Board www.xilinx.com 45
UG952 (v1.1) January 30, 2013
Feature Descriptions
Table 1-21 lists the connections between the FPGA and the LCD header. If the LCD is not
installed, the J23 pins listed in Table 1-21 can be used for GPIO.
References
The datasheet for the Displaytech S162DBABC LCD can be found at
http://www.displaytech-us.com/products/charactermodules.php. Choose the S162D
model full spec download arrow.
I
2
C Bus Switch
[Figure 1-2, callout 19]
The AC701 board implements a single I
2
C port on FPGA Bank 14 ( IIC_SDA_MAIN, FPGA
pin K25 and IIC_SCL_MAIN, FPGA pin N18), which is routed through a Texas
Instruments PCA9548 1-to-8 channel I
2
C switch (U52). The I
2
C switch can operate at
speeds up to 400
kHz. The U52 bus switch at I
2
C address 0x74/0b01110100 must be
addressed and configured to select the desired target downstream device.
The AC701 board I
2
C bus topology is shown in Figure 1-27.
User applications that communicate with devices on one of the downstream I
2
C buses
must first set up a path to the desired bus through the U52 bus switch at I
2
C address 0x74/
0b01110100.
Table 1-21: FPGA to LCD Header Connections
FPGA Pin
(U1)
Schematic Net
Name
LCD Header Pin
(J23)
L25 LCD_DB4_LS 4
M24 LCD_DB5_LS 3
M25 LCD_DB6_LS 2
L22 LCD_DB7_LS 1
L24 LCD_RW_LS 10
L23 LCD_RS_LS 11
L20 LCD_E_LS 9
X-Ref Target - Figure 1-27
Figure 1-27: I
2
C Bus Topology
PCA9548
1
2
C 1-to-8
Bus Switch
CH7 - SI5324_SDA/SCL
U52
IIC_SDA/SCL_MAIN
CH6 - IIC_SDA/SCL_DDR3
CH5 - IIC_SDA/SCL_HDMI
CH4 - SFP_IIC_SDA/SCL
CH3 - EEPROM_IIC_SDA/SCL
CH2 - (NOT USED)
CH1 - FMC_HPC_IIC_SDA/SCL
CH0 - USER_CLK_SDL/SCL
FPGA
Bank 14
(3.3V)
0x74
U1
UG952_C1_27_100312