User guide

54 www.xilinx.com AC701 Evaluation Board
UG952 (v1.1) January 30, 2013
Chapter 1: AC701 Evaluation Board Features
Configuration Mode Switch SW1
The AC701 board supports two of the five 7 series FPGA configuration modes:
• Master SPI using the on-board Quad SPI flash memory
• JTAG using a standard-A to micro-B USB cable for connecting the host PC to the
AC701 board configuration port (via Digilent module)
Each configuration interface corresponds to one or more configuration modes and bus
widths as listed in
Table 1-25. The mode switches M2, M1, and M0 are on SW1 positions 1,
2, and 3 respectively as shown in Figure 1-39.
Note: On the AC701 board, SW1 switch position 2 is not used.
The default mode setting is M[2:0] = 001, which selects Master SPI at board power-on.
See UG470, 7 Series FPGAs Configuration User Guide for further details on configuring the 7
series FPGAs.
FPGA Mezzanine Card Interface
[Figure 1-2, callout 29]
The AC701 board supports the VITA 57.1 FPGA Mezzanine Card (FMC) specification by
providing high pin count (HPC) connector J30. HPC J30 is keyed so that a the mezzanine
card faces away from the AC701 board when connected.
Signaling Speed Ratings:
• Single-ended: 9 GHz (18 Gb/s)
• Differential Optimal Vertical: 9 GHz (18 Gb/s)
• Differential Optimal Horizontal: 16 GHz (32 Gb/s)
• High Density Vertical: 7 GHz (15 Gb/s)
X-Ref Target - Figure 1-39
Figure 1-39: Mode Switch SW1
Table 1-25: AC701 Board FPGA Configuration Modes
Configuration Mode
SW13 DIP Switch
Settings (M[2:0])
Bus Width CCLK Direction
Master SPI 001 x1, x2, x4 Output
JTAG 101 x1 Not Applicable
R339
1.21K 1%
1/10W
R338
1.21K 1%
1/10W
R337
1.21K 1%
1/10W
FPGA_3V3
SW1
1
2
3
6
5
4
SDA03H1SBD
FPGA_M2
FPGA_M1
FPGA_M0
UG952_c1_36_011713
NC