User guide

AC701 Evaluation Board www.xilinx.com 63
UG952 (v1.1) January 30, 2013
Feature Descriptions
Figure 1-41 shows the power system for UCD90120A U9 controller #2 rails 1 through 5.
X-Ref Target - Figure 1-41
Figure 1-41: U9 Controller #2 UCD90120A Power System
UG952_c1_138_011513
UCD90120A
Controller
(Controller 2)
U9
1. Capacitors labled C
f
are bulk filter capacitors.
2. Voltage Sense is connected
GPIO (Out)
FPWM (Out)
ADC (In)
ADC (In)
GPIO (Out)
Input
Filter
TPS84621
U49 (2.5V Nom)
Vin Vout
EN
FB
Rail Enable
PWM Margin
Current Sense
Voltage Sense
(2)
FMC_ADJ_SEL[1:0]
Rs 5mΩ
+12V
V
fb
VCCO_ADJ 2.5V
C
f
C
f
(1)
G = 125.07
VCCO_VADJ
0A-3.2A
CS = 0V-2.00V
Notes:
GPIO (Out)
FPWM (Out)
ADC (In)
ADC (In)
Input
Filter
TPS84320
U57 (1.8V Nom)
Vin Vout
EN
FB
Rail Enable
PWM Margin
Current Sense
Voltage Sense
(2)
Rs 5mΩ
+12V
V
fb
FPGA_1V8 1.8V
C
f
C
f
G = 125.07
FPGA_1V8
0A-3.2A
CS = 0V-2.00V
VCC1V8 1.8V
GPIO (Out)
FPWM (Out)
ADC (In)
ADC (In)
Input
Filter
TPS84321
U58 (3.3V Nom)
Vin Vout
EN
FB
Rail Enable
PWM Margin
Current Sense
Voltage Sense
(2)
Rs 5mΩ
+12V
V
fb
FPGA_3V3 3.3V
C
f
C
f
G = 125.07
FPGA_3V3
0A-3.2A
CS = 0V-2.00V
VCC3V3 3.3V
GPIO (Out)
FPWM (Out)
ADC (In)
ADC (In)
Input
Filter
TPS84320
U59 (1.0V Nom)
Vin Vout
EN
FB
Rail Enable
PWM Margin
Current Sense
Voltage Sense
(2)
Rs 5mΩ
+12V
V
fb
C
f
C
f
G = 134.3
MGTAVCC
0A-3.0A
CS = 0V-2.02V
MGTAVCC 1.0V
GPIO (Out)
FPWM (Out)
ADC (In)
ADC (In)
Input
Filter
TPS84320
U60 (1.2V Nom)
Vin Vout
EN
FB
Rail Enable
PWM Margin
Current Sense
Voltage Sense
(2)
Rs 5mΩ
+12V
V
fb
MGTAVTT 1.2V
C
f
C
f
G = 268.4
MGTAVTT
0A-1.5A
CS = 0V-2.02V
U64
I0B
I1B
I2B
I3B
YB
S[1:0]
FMC_ADJ_SEL[1:0]
Value
0 0
0 1
1 0
1 1
VCCO_ADJ
Output
2.5V
1.8V
3.3V
3.3V
at point of load.
(Not measued separately)
(Not measued separately)