User guide

AC701 Board XDC File Listing
AC701 Evaluation Board www.xilinx.com 95
UG952 (v1.1) January 30, 2013
set_property PACKAGE_PIN U2 [get_ports DDR3_ODT1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT1]
set_property PACKAGE_PIN U1 [get_ports DDR3_TEMP_EVENT]
set_property IOSTANDARD LVCMOS15 [get_ports DDR3_TEMP_EVENT]
set_property PACKAGE_PIN P6 [get_ports GPIO_SW_N]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_SW_N]
set_property PACKAGE_PIN P5 [get_ports VTTVREF]
set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
set_property PACKAGE_PIN T5 [get_ports GPIO_SW_S]
set_property IOSTANDARD SSTL15 [get_ports GPIO_SW_S]
set_property PACKAGE_PIN R5 [get_ports GPIO_SW_W]
set_property IOSTANDARD SSTL15 [get_ports GPIO_SW_W]
set_property PACKAGE_PIN U6 [get_ports GPIO_SW_C]
set_property IOSTANDARD SSTL15 [get_ports GPIO_SW_C]
set_property PACKAGE_PIN U5 [get_ports GPIO_SW_E]
set_property IOSTANDARD SSTL15 [get_ports GPIO_SW_E]
set_property PACKAGE_PIN R8 [get_ports GPIO_DIP_SW0]
set_property IOSTANDARD SSTL15 [get_ports GPIO_DIP_SW0]
set_property PACKAGE_PIN P8 [get_ports GPIO_DIP_SW1]
set_property IOSTANDARD SSTL15 [get_ports GPIO_DIP_SW1]
set_property PACKAGE_PIN R7 [get_ports GPIO_DIP_SW2]
set_property IOSTANDARD SSTL15 [get_ports GPIO_DIP_SW2]
set_property PACKAGE_PIN R6 [get_ports GPIO_DIP_SW3]
set_property IOSTANDARD SSTL15 [get_ports GPIO_DIP_SW3]
set_property PACKAGE_PIN T8 [get_ports USER_SMA_GPIO_P]
set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_GPIO_P]
set_property PACKAGE_PIN T7 [get_ports USER_SMA_GPIO_N]
set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_GPIO_N]
set_property PACKAGE_PIN U4 [get_ports CPU_RESET]
set_property IOSTANDARD LVCMOS15 [get_ports CPU_RESET]
set_property PACKAGE_PIN J8 [get_ports No]
set_property IOSTANDARD SSTL15 [get_ports No]
set_property PACKAGE_PIN E6 [get_ports DDR3_D63]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D63]
set_property PACKAGE_PIN D6 [get_ports DDR3_D62]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D62]
set_property PACKAGE_PIN H8 [get_ports DDR3_D61]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D61]
set_property PACKAGE_PIN G8 [get_ports DDR3_D60]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D60]
set_property PACKAGE_PIN H7 [get_ports DDR3_DQS7_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_P]
set_property PACKAGE_PIN G7 [get_ports DDR3_DQS7_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_N]
set_property PACKAGE_PIN F8 [get_ports DDR3_D59]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D59]
set_property PACKAGE_PIN F7 [get_ports DDR3_D58]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D58]
set_property PACKAGE_PIN H6 [get_ports DDR3_D57]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D57]
set_property PACKAGE_PIN G6 [get_ports DDR3_D56]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D56]
set_property PACKAGE_PIN H9 [get_ports DDR3_DM7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM7]
set_property PACKAGE_PIN G9 [get_ports VTTVREF]
set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
set_property PACKAGE_PIN J6 [get_ports DDR3_D55]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D55]
set_property PACKAGE_PIN J5 [get_ports DDR3_D54]