- Silicon Laboratories, Inc. Clock User Manual

ManualsBrandsSilicon Laboratories ManualsClockSI5326

ANY-FREQUENCY PRECISION CLOCKS

Si5316, Si5319, Si5322, Si5323, Si5324, Si5325,

Si5326, Si5327, Si5365, Si5366, Si5367,

Si5368, Si5369, Si5374, Si5375

AMILY REFERENCE MANUAL

Summary of content (180 pages)

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A NY - F R E Q U E N C Y P RECISION C L O C K S Si5316, Si5319, Si5322, S i 5 3 2 3 , S i 5 3 2 4 , S i 5 3 2 5 , Si5326, Si5327, Si5365, Si5366, Si5367, Si5368, Si5369, Si5374, Si5375 F AMILY R EFERENCE M ANUAL Rev. 0.
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Si53xx-RM 2 Rev. 0.
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Si53xx-RM TABLE O F C ONTENTS Section Page 1. Any-Frequency Precision Clock Product Family Overview . . . . . . . . . . . . . . . . . . . . . . 12 2. Narrowband vs. Wideband Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3. Any-Frequency Clock Family Members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1. Si5316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Si53xx-RM 6.3.1. Manual Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.2. Automatic Clock Selection (Si5322, Si5323, Si5365, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.3. Hitless Switching with Phase Build-Out (Si5323, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.4. Digital Hold/VCO Freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Si53xx-RM and Si5375 Free Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.5.1. Free Run Mode Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.2. Clock Control Logic in Free Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.3. Free Run Reference Frequency Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.4.
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Si53xx-RM 8.2.1. LVPECL TQFP Output Signal Format Restrictions at 3.3 V (Si5367, Si5368, Si5369) . . . . . . 107 8.2.2. Typical Output Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.2.3. Typical Clock Output Scope Shots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.3. Typical Scope Shots for SFOUT Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.4.
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Si53xx-RM L I S T OF F IGURES Figure 1. Si5316 Any-Frequency Jitter Attenuator Block Diagram . . . . . . . . . . . . . . . . . . . . . 17 Figure 2. Si5319 Any-Frequency Jitter Attenuating Clock Multiplier Block Diagram . . . . . . . . 18 Figure 3. Si5322 Low Jitter Clock Multiplier Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 4. Si5323 Jitter Attenuating Clock Multiplier Block Diagram . . . . . . . . . . . . . . . . . . . . 20 Figure 5.
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Si53xx-RM Figure 43. Differential Output Example Requiring Attenuation . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 44. Typical CMOS Output Circuit (Tie CKOUTn+ and CKOUTn– Together) . . . . . . . 108 Figure 45. CKOUT Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 46. sfout_2, CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 47. sfout_3, lowSwingLVDS. . . .
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Si53xx-RM Figure 88. RF Generator, Si5326, Si5324; No Jitter (For Reference) . . . . . . . . . . . . . . . . . . 165 Figure 89. RF Generator, Si5326, Si5324 (50 Hz Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Figure 90. RF Generator, Si5326, Si5324 (100 Hz Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Figure 91. RF Generator, Si5326, Si5324 (500 Hz Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Figure 92.
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Si53xx-RM L I S T OF TABLES Table 1. Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2. Product Selection Guide (Si5322/25/65/67) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3. Recommended Operating Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Si53xx-RM Table 42. Digital Hold History Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 43. Digital Hold History Averaging Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 44. CKIN3/CKIN4 Frequency Selection (CK_CONF = 1) . . . . . . . . . . . . . . . . . . . . . . . 92 Table 45. Common NC5 Divider Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 46.
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Si53xx-RM 1. Any-Frequency Precision Clock Product Family Overview Silicon Laboratories Any-Frequency Precision Clock products provide jitter attenuation and clock multiplication/ clock division for applications requiring sub 1 ps rms jitter performance.
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Si53xx-RM A wide range of settings are available, but they are a subset of the frequency plans supported by the Si5323 and Si5366 jitter-attenuating clock multipliers. The Si5325 and Si5367 are microprocessor-controlled clock multipliers that can be controlled via an I2C or SPI interface. These devices accept clock inputs ranging from 10 MHz to 710 MHz and generate multiple independent, synchronous clock outputs ranging from 10 MHz to 945 MHz and select frequencies to 1.4 GHz.
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Si53xx-RM Table 1. Product Selection Guide Part Number Control Number of Input Output RMS Phase Jitter PLL Hitless Inputs and Frequency Frequency (12 kHz–20 MHz) Bandwidth Switching Outputs (MHz)* (MHz)* Free Run Mode  Package 0.008–644 0.45 ps 60 Hz to 8 kHz 19–710 19–710 0.3 ps 60 Hz to 8 kHz 6x6 mm 36-QFN 1–710 1–710 0.3 ps 60 Hz to 8 kHz 6x6 mm 36-QFN 1PLL, 1 | 1 0.002–710 0.002–1417 0.3 ps 60 Hz to 8 kHz Pin 1PLL, 2 | 2 0.008–707 0.008–1050 0.
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Si53xx-RM 1.8, 2.5 V Operation 1.8, 2.5, 3.3 V Operation 100 Lead 14 x 14 mm TQFP 36 Lead 6 mm x 6 mm QFN FSYNC Realignment LOL Alarm FOS Alarm Hitless Switching LOS Jitter Generation (12 kHz – 20 MHz) Max Output Frequency (MHz) Max Input Freq (MHz)1 P Control Clock Outputs Clock Inputs Device Table 2. Product Selection Guide (Si5322/25/65/67) Low Jitter Precision Clock Multipliers (Wideband) Si5322 2 2 Si5325 2 2 Si5365 4 5 Si5367 4 5   707 1050 0.
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Si53xx-RM 2. Narrowband vs.
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Si53xx-RM 3. Any-Frequency Clock Family Members 3.1. Si5316 The Si5316 is a low jitter, precision jitter attenuator for high-speed communication systems, including OC-48, OC192, 10G Ethernet, and 10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38, 77, 155, 311, or 622 MHz frequency range and generates a jitter-attenuated clock output at the same frequency.
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Si53xx-RM 3.2. Si5319 The Si5319 is a jitter-attenuating precision M/N clock multiplier for applications requiring sub 1 ps jitter performance. The Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5319 can also use its crystal oscillator as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range.
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Si53xx-RM 3.3. Si5322 The Si5322 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5322 accepts dual clock inputs ranging from 19.44 to 707 MHz and generates two frequencymultiplied clock outputs ranging from 19.44 to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel, and broadcast video (HD SDI, 3G SDI) rates.
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Si53xx-RM 3.4. Si5323 The Si5323 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, Fibre Channel, and broadcast video (HD SDI, 3G SDI). The Si5323 accepts dual clock inputs ranging from 8 kHz to 707 MHz and generates two frequency-multiplied clock outputs ranging from 8 kHz to 1050 MHz.
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Si53xx-RM 3.5. Si5324 The Si5324 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5324 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range.
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Si53xx-RM 3.6. Si5325 The Si5325 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5325 accepts dual clock inputs ranging from 10 to 710 MHz and generates two independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5325 input clock frequency and clock multiplication ratios are programmable through an I2C or SPI interface.
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Si53xx-RM 3.7. Si5326 The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5326 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range.
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Si53xx-RM 3.8. Si5327 The Si5327 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5327 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two independent, synchronous clock outputs ranging from 2 kHz to 808 MHz. The device provides virtually any frequency translation combination across this operating range. The Si5327 input clock frequency and clock multiplication ratios are programmable through an I2C or SPI interface.
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Si53xx-RM 3.9. Si5365 The Si5365 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5365 accepts four clock inputs ranging from 19.44 MHz to 707 MHz and generates five frequency-multiplied clock outputs ranging from 19.44 MHz to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel, and broadcast video rates.
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Si53xx-RM 3.10. Si5366 The Si5366 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5366 accepts four clock inputs ranging from 8 kHz to 707 MHz and generates five frequency-multiplied clock outputs ranging from 8 kHz to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel, and broadcast video (HD SDI, 3G SDI) rates.
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Si53xx-RM 3.11. Si5367 The Si5367 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5367 accepts four clock inputs ranging from 10 to 707 MHz and generates five frequencymultiplied clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5367 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface.
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Si53xx-RM 3.12. Si5368 The Si5368 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance. The Si5368 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range.
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Si53xx-RM 3.13. Si5369 The Si5369 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance. The Si5369 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range.
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Si53xx-RM 3.15. Si5374 The Si5374 is a highly integrated, 4-PLL jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. Each of the DSPLL® clock multiplier engines accepts two input clocks ranging from 2 kHz to 710 MHz and generates two independent, synchronous output clocks ranging from 2 kHz to 808 MHz. Each DSPLL provides virtually any frequency translation across this operating range.
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Si53xx-RM 3.16. Si5375 The Si5375 is a highly integrated, 4-PLL jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. Each of the DSPLL® clock multiplier engines accepts an input clock ranging from 2 kHz to 710 MHz and generates an output clock ranging from 2 kHz to 808 MHz. Each DSPLL provides virtually any frequency translation combination across this operating range.
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Si53xx-RM 4. Device Specifications The following tables are intended to simplify device selection. The specifications in the individual device data sheets take precedence over this document. Refer to the respective device data sheet for devices not listed in the tables below. Si5325 Si5365 Si5366 Si5367 Si5368 Supply Voltage During Normal Operation Si5324 Ambient Temperature Si5322 Parameter Si5316 Table 3. Recommended Operating Conditions1         3.3 V Nominal     2.
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Si53xx-RM LVPECL Format 622.08 MHz Out Only 1 CKOUT Enabled           Disable Mode    1.8 V ± 10%   2.5 V ± 10%  3.3 V ± 10%       CMOS Format 19.44 MHz Out Only 1 CKOUT Enabled    CMOS Format 19.44 MHz Out All CKOUTs Enabled  Si5368  Si5367  Si5366 LVPECL Format 622.08 MHz Out All CKOUT’s Enabled Si5365 IDD Si5325 Test Condition Si5324 Supply Current (Independent of Supply Voltage) Symbol Si5322 Parameter Si5316 Table 4.
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Si53xx-RM Si5368 Si5367 Si5366 Si5365 Si5325 Test Condition Si5324 Symbol Si5322 Parameter Si5316 Table 4. DC Characteristics (Continued) Min Typ Max Units Output Clocks (CKOUTn—See “8.2. Output Clock Drivers” for Configuring Output Drivers for LVPECL/CML/LVDS/CMOS) Common Mode VOCM LVPECL 100  load line-to-line         VDD – — VDD – 1.42 V 1.25 Differential Output Swing VOD LVPECL 100  load line-to-line1         1.1 — 1.
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Si53xx-RM Si5366 Si5367 Si5368 CMOS Driving into CKOVOL for output low or CKOVOH for output high. CKOUT+ and CKOUT– shorted externally. Si5365 CKOIO Si5325 Test Condition Si5324 Output Drive Current (CMOS driving into CKOVOL for output low or CKOVOH for output high. CKOUT+ and CKOUT- shorted externally) Symbol Si5322 Parameter Si5316 Table 4. DC Characteristics (Continued) Min         — Typ Max Units VDD = 1.8 V ICMOS[1:0] = 11 7.5 — mA    — 5.
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Si53xx-RM Si5322 Si5324 Si5325 Si5365 Si5366 Si5368 Test Condition Input Mid Current IIMM See note 2       Input High Current IIHH See note 2       VOL IO = 2 mA VDD = 1.62 V      IO = 2 mA VDD = 2.97 V     IO = –2 mA VDD = 1.62 V     IO = –2 mA VDD = 2.97 V  RST = 0  Parameter Si5367 Symbol Si5316 Table 4. DC Characteristics (Continued) Min Typ Max Units   –2 — 2 µA   — — 20 µA    — — 0.
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Si53xx-RM Table 5. DC Characteristics—Microprocessor Devices (Si5324, Si5325, Si5367, Si5368) Parameter Symbol Test Condition Min Typ Max Units I2C Bus Lines (SDA, SCL) Input Voltage Low VILI2C — — 0.25 x VDD V Input Voltage High VIHI2C 0.7 x VDD — VDD V Input Current III2C VIN = 0.1 x VDD to 0.9 x VDD –10 — 10 µA Hysteresis of Schmitt trigger inputs VHYSI2C VDD = 1.8 V 0.1 x VDD — — V VDD = 2.5 or 3.3 V 0.05 x VDD — — V Output Voltage Low VOHI2C VDD = 1.
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Si53xx-RM tc tr tf SCLK thsc tlsc tsu1 th1 SS tcs tsu2 th2 SDI td1 td3 td2 SDO Figure 18. SPI Timing Diagram Table 7. DC Characteristics—Narrowband Devices (Si5316, Si5319, Si5323, Si5366, Si5368) Parameter Symbol Test Condition Min Typ Max Unit — 10 — k Single-Ended Reference Clock Input Pin XA (XB with cap to gnd) Input Resistance XARIN Input Voltage Level Limits XAVIN 0 — 1.2 V Input Voltage Swing XAVPP 0.5 — 1.2 VPP 0 — 1.2 V 0.5 — 2.
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Si53xx-RM CLKOUT_2 1/f FSYNC CLKIN_4* t FSSU tFSH FSYNC_ALIGN t LATF FSYNCOUT* Fixed number of CLKOUT_2 clock cycles. * CLKIN_2 and CLKIN_4 are the active input clock and frame sync pair in this example Figure 19. Frame Synchronization Timing Rev. 0.
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Si53xx-RM Si5367 Si5368 Test Condition Si5325 Si5365 Si5366 Symbol Si5322 Si5324 Parameter Si5316 Table 8. AC Characteristics—All Devices Min Typ Max Units 19.38 — 710 MHz 19.43 — 707.35 MHz  0.002 — 707.35 MHz 10 — 710 MHz — 0.008 — MHz  2 — 512 kHz  Input Frequency    CKNF     When used as frame synchronization input CKIN_n Input Pins Input Duty Cycle (Minimum Pulse Width) Whichever is smaller (i.e.
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Si53xx-RM Si5367 Si5368 Test Condition Si5325 Si5365 Si5366 Symbol Si5322 Si5324 Parameter Si5316 Table 8. AC Characteristics—All Devices (Continued) Min Typ Max Units — — 3 pF 1 — — µs — — 10 ms 100 x N3 — 570 x N3 TCKIN 0.
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Si53xx-RM tSKEW of CKOUT_n to of CKOUT_m, CKOUT_n and CKOUT_m at same frequency and signal format PHASE OFFSET = 0 SQICAL = 1 CKOUT_ALWAYS_O N=1 Coarse Skew Adjust Resolution tPHRES Using CLAT[7:0] register Si5367 Si5368 Output Clock Skew, see Section 7.7.4 Si5325 Si5365 Si5366 Test Condition Si5322 Si5324 Symbol Parameter Si5316 Table 8.
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Si53xx-RM Output Phase Change due to Temperature Variation Jitter Tolerance Phase Noise fout = 622.08 MHz tTEMP Max phase changes from –40 to +85 °C Spurious Noise SPSPUR Typ Max Units — 300 500 ps See "5.2.3. Jitter Tolerance" on page 49.
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Si53xx-RM Table 9. Jitter Generation (Si5316, Si5324, Si5366, Si5368) Parameter Symbol Test Condition1,2,3,4,5 Min Typ Max GR-253 Spec Unit — 4.2 6.2 30 ps pp/0.3 UIpp psPP — .27 .42 N/A psrms — 3.7 6.4 10 ps pp/0.1 UIpp psPP — .14 .31 N/A psrms — 4.4 6.9 10 ps pp/0.1 UIpp psPP — .26 .41 1.0 psrms (0.01 UIrms psrms — 3.5 5.4 40.2 ps pp/ (0.1 UIpp) psPP — .27 .41 4.02 psrms (0.01 UIrms psrms Measurement DSPLL Filter (MHz) Bandwidth2 0.
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Si53xx-RM Table 11. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol Test Condition Devices Value Unit JA Still Air Si5316, Si5319, Si5322, Si5323, Si5324, Si5325 32 ºC/W Si5365, Si5366, Si5367, Si5368 40 ºC/W Si5316, Si5319, Si5322, Si5323, Si5324, Si5325 14 ºC/W JC Still Air Rev. 0.
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Si53xx-RM 5. DSPLL (All Devices) All members of the Any-Frequency Precision Clocks family incorporate a phase-locked loop (PLL) that utilizes Silicon Laboratories' third generation DSPLL technology to eliminate jitter, noise, and the need for external VCXO and loop filter components found in discrete PLL implementations. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in discrete PLL designs.
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Si53xx-RM 5.1. Clock Multiplication Fundamental to these parts is a clock multiplication circuit that is simplified in Figure 21. By having a large range of dividers and multipliers, nearly any output frequency can be created from a fixed input frequency. For typical telecommunications and data communications applications, the hardware control parts (Si5316, Si5322, Si5323, Si5365, and Si5366) provide simple pin control.
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Si53xx-RM 5.2. PLL Performance All members of the Any-Frequency Precision Clock family of devices provide extremely low jitter generation, a wellcontrolled jitter transfer function, and high jitter tolerance. For more information the loop bandwidth and its effect on jitter attenuation, see "Appendix H—Jitter Attenuation and Loop BW" on page 164. 5.2.1. Jitter Generation Jitter generation is defined as the amount of jitter produced at the output of the device with a jitter free input clock.
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Si53xx-RM 5.2.3. Jitter Tolerance Jitter tolerance is defined as the maximum peak-to-peak sinusoidal jitter that can be present on the incoming clock before the DSPLL loses lock. The tolerance is a function of the jitter frequency, because tolerance improves for lower input jitter frequency. The jitter tolerance of the DSPLL is a function of the loop bandwidth setting. Figure 23 shows the general shape of the jitter tolerance curve versus input jitter frequency.
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Si53xx-RM 6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366) These parts provide high-performance clock multiplication with simple pin control. Many of the control inputs are three levels: High, Low, and Medium. High and Low are standard voltage levels determined by the supply voltage: VDD and Ground. If the input pin is left floating, it is driven to nominally half of VDD. Effectively, this creates three logic levels for these controls.
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Si53xx-RM The Si5316 can accept a CKIN1 input at a different frequency than the CKIN2 input. The frequency of one input clock can be 1x, 4x, or 32x the frequency of the other input clock. The output frequency is always equal to the lower of the two clock inputs and is set via the FRQSEL [1:0] pins. The frequency applied at each clock input is divided down by a pre-divider as shown in the Figure 1 on page 17.
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Si53xx-RM 6.1.2. Clock Multiplication (Si5322, Si5323, Si5365, Si5366) These parts provide flexible frequency plans for SONET, DATACOM, and interworking between the two (Table 16, Table 17, and Table 18 respectively). The CKINn inputs must be the same frequency as specified in the tables. The outputs are the same frequency; however, in the Si5365 and Si5366, CKOUT3 and CKOUT4 can be further divided down by using the DIV34 [1:0] pins. The following notes apply to Tables 16, 17, and 18: 1.
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Si53xx-RM Table 16. SONET Clock Multiplication Settings (FRQTBL=L) (Continued) FRQSEL [3:0] fIN MHz Mult Factor Nominal fOUT MHz WB No 7 LLHM  8 LLHH 9 19.44 All Devices Si5366 Only fCKOUT5 (MHz) (CK_CONF = 0) FS_OUT (MHz) (CK_CONF = 1) 1 19.44 19.44 0.008  2 38.88 38.88 0.008 LMLL  4 77.76 77.76 0.008 10 LMLM  8 155.52 155.52 0.008 11 LMLH 8 x (255/238) 166.63 166.63 NA 12 LMML 8 x (255/237) 167.33 167.33 NA 13 LMMM 8 x (255/236) 168.04 168.
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Si53xx-RM Table 16. SONET Clock Multiplication Settings (FRQTBL=L) (Continued) 54 FRQSEL [3:0] fIN MHz Mult Factor Nominal fOUT MHz WB No 28 MLLM  29 MLLH 30 77.76 All Devices Si5366 Only fCKOUT5 (MHz) (CK_CONF = 0) FS_OUT (MHz) (CK_CONF = 1) 1/4 19.44 19.44 0.008  1/2 38.88 38.88 0.008 MLML  1 77.76 77.76 0.008 31 MLMM  2 155.52 155.52 0.008 32 MLMH  2 x (255/238) 166.63 166.63 NA 33 MLHL 2 x (255/237) 167.33 167.33 NA 34 MLHM 2 x (255/236) 168.
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Si53xx-RM Table 16. SONET Clock Multiplication Settings (FRQTBL=L) (Continued) FRQSEL [3:0] fIN MHz Mult Factor Nominal fOUT MHz WB No 56 HLLL 167.33 57 MMHM 58 HLLM 59 MHML 60 HLLH 61 MMHM 62 HLML 63 MHML  64 HLMM  65 HLMH 66 HLHL 67 All Devices Si5366 Only fCKOUT5 (MHz) (CK_CONF = 0) FS_OUT (MHz) (CK_CONF = 1) 237/255 155.52 155.52 NA 1 167.33 167.33 NA 4 x (237/255) 622.08 622.08 NA 4 669.33 669.33 NA 236/255 155.52 155.52 NA 1 168.04 168.
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Si53xx-RM Table 16. SONET Clock Multiplication Settings (FRQTBL=L) (Continued) 56 FRQSEL [3:0] 82 HHLH 83 HMML 84 HHML 85 HMMH 86 HHMM 87 HMML 88 HHMH 89 HMMH fIN MHz Mult Factor Nominal fOUT MHz WB No 669.33   672.16   All Devices Si5366 Only fCKOUT5 (MHz) (CK_CONF = 0) FS_OUT (MHz) (CK_CONF = 1) 1/4 x 237/255 155.52 155.52 NA 1/4 167.33 167.33 NA 237/255 622.08 622.08 NA 1 669.33 669.33 NA 1/4 x 236/255 155.52 155.52 NA 1/4 168.04 168.
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Si53xx-RM Setting FRQSEL[3:0] WB Table 17. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF = 0) fIN (MHz) Mult Factor fOUT* (MHz)       15.625 2 31.25 4 62.5 8 125 16 250 17/4 106.25 5 125 0 LLLL 1 LLLM 2 LLLH 3 LLML 4 LLMM 5 LLMH 6 LLHL 25/4 x 66/64 161.13 7 LLHM 51/8 x 66/64 164.36 8 LLHH 25/4 x 66/64 x 255/238 172.64 9 LMLL 25/4 x 66/64 x 255/237 173.37 10 LMLM 51/8 x 66/64 x 255/238 176.1 11 LMLH 51/8 x 66/64 x 255/237 176.
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Si53xx-RM Setting FRQSEL[3:0] 58 WB Table 17. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF = 0) (Continued) fIN (MHz) Mult Factor fOUT* (MHz)  125 10/8 x 66/64 161.13 172.64 34 MLHM 35 MLHH 10/8 x 66/64 x 255/238 36 MMLL 10/8 x 66/64 x 255/237 173.37 37 MMLM 5 x 66/64 644.53 38 MMLH 5 x 66/64 x 255/238 690.57 39 MMML 5 x 66/64 x 255/237 693.48 40 MMMM 66/64 161.13 41 MMMH 66/64 x 255/238 172.64 42 MMHL 66/64 x 255/237 173.37 43 MMHM 4 x 66/64 644.
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Si53xx-RM Setting FRQSEL[3:0] 69 HLML 70 HLMM 71 HLMH 72 HLHL 73 MHMM 74 HLHM 75 HLLL 76 HLLM 77 HLLH 78 MHMM 79 HLHH 80 HLMM 81 HLMH 82 HLHL 83 MHMM 84 HMLL 85 HMLM 86 HMLH 87 HMML 88 HMMM 89 HMMH 90 HMHL 91 HMHM 92 HMML 93 HMMM 94 HMMH 95 HMHL 96 HMHH 97 HHLL 98 HHLM 99 HMML 100 HHLH 101 HMMM WB Table 17. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF = 0) (Continued) fIN (MHz) Mult Factor fOUT* (MHz) 173.
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Si53xx-RM Setting FRQSEL[3:0] 60 102 HHML 103 HHMM 104 HHMH 105 HMML 106 HHHL 107 HMMM 108 HHHM 109 HHLL 110 HHLM 111 HMML 112 HHLH 113 HMMM 114 HHHH 115 HHMM 116 HHMH 117 HMML 118 HHHL 119 HMMM WB Table 17. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF = 0) (Continued) fIN (MHz) Mult Factor fOUT* (MHz) 693.48 1/5 x 64/66 x 237/255 125 1/4 x 64/66 x 237/255 156.25 1/4 x 237/255 161.13 1/4 173.37 237/255 644.53 1 693.
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Si53xx-RM Setting FRQSEL[3:0] WB Table 18. SONET to Datacom Clock Multiplication Settings fIN (MHz) Mult Factor fOUT* (MHz) 0.008 3125 25 0 LLLL 1 LLLM 6480 51.84 2 LLLH 53125/8 53.125 3 LLML 15625/2 62.5 4 LLMM 53125/4 106.25 5 LLMH 15625 125 6 LLHL 78125/4 156.25 7 LLHM 159375/8 159.375 8 LLHH 53125/2 212.5 9 LMLL 53125 425 10 LMLM 625/486 25 11 LMLH 10625/3888 53.125 12 LMML 3125/972 62.5 13 LMMM 10625/1944 106.
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Si53xx-RM WB Table 18. SONET to Datacom Clock Multiplication Settings (Continued) fIN (MHz) 30 MLML  62.500 31 MLMM  32 MLMH 33 MLHL 1 74.17582 34 MLHM 91 x 11/250 x 4 74.25 35 MLHH 4/11 27 36 MMLL 4 x 250/11 x 91 74.17582 37 MMLM 1 74.25 38 MMLH 10625/7776 106.25 39 MMML 3125/1944 125 40 MMMM 15625/7776 156.25 41 MMMH 31875/15552 159.375 42 MMHL 15625/7776 x 66/64 161.13 43 MMHM 31875/15552 x 66/64 164.36 44 MMHH 15625/7776 x 66/ 64 x 255/238 172.
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Si53xx-RM Setting FRQSEL[3:0] WB Table 18. SONET to Datacom Clock Multiplication Settings (Continued) fIN (MHz) Mult Factor fOUT* (MHz) 155.520 15625/15552 156.25 52 MHHM 53 MHHH 31875/31104 159.375 54 HLLL 15625/15552 x 66/64 161.13 55 HLLM 31875/31104 x 66/64 164.36 56 HLLH 15625/15552 x 66/ 64 x 255/238 172.64 57 HLML 31875/31104 x 66/ 64 x 255/238 176.1 58 HLMM 10625/7776 212.5 59 HLMH 10625/3888 425 60 HLHL 15625/3888 x 66/64 644.
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Si53xx-RM 6.1.3. CKOUT3 and CKOUT4 (Si5365 and Si5366) Submultiples of the output frequency on CKOUT1 and CKOUT2 can be produced on the CKOUT3 and CKOUT4 outputs using the DIV34 [1:0] control pins as shown in Table 19. Table 19. Clock Output Divider Control (DIV34) DIV34[1:0] Output Divider Value HH 32 HM 16 HL 10 MH 8 MM 6 ML 5 LH 4 LM 2 LL 1 6.1.4.
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Si53xx-RM 6.2. PLL Self-Calibration An internal self-calibration (ICAL) is performed before operation to optimize loop parameters and jitter performance. While the self-calibration is being performed, the DSPLL is being internally controlled by the selfcalibration state machine, and the LOL alarm will be active for narrowband parts. The self-calibration time tLOCKHW is given in Table 8, “AC Characteristics—All Devices”.
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Si53xx-RM Table 20.
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Si53xx-RM 6.3. Pin Control Input Clock Control This section describes the clock selection capabilities (manual input selection, automatic input selection, hitless switching, and revertive switching). When switching between two clocks, LOL may temporarily go high if the two clocks differ in frequency by more than 100 ppm. 6.3.1. Manual Clock Selection Manual control of input clock selection is chosen via the CS[1:0] pins according to Table 22 and Table 23. Table 22.
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Si53xx-RM 6.3.2. Automatic Clock Selection (Si5322, Si5323, Si5365, Si5366) The AUTOSEL input pin sets the input clock selection mode as shown in Table 24. Automatic switching is either revertive or non-revertive. Setting AUTOSEL to M or H, changes the CSn_CAm pins to output pins that indicate the state of the automatic clock selection (See Table 25 and Table 26). Digital hold is indicated by all CnB signals going high after a valid ICAL. Table 24.
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Si53xx-RM Table 28. Input Clock Priority for Auto Switching (Si5365, Si5366) Priority Input Clock Configuration Si5365 Si5366 4 Input Clocks (CK_CONF = 0) FSYNC Switching (CK_CONF = 1) 1 CKIN1 CKIN1/CKIN3 2 CKIN2 CKIN2/CKIN4 3 CKIN3 N/A 4 CKIN4 N/A 5 Digital Hold Digital Hold At power-on or reset, the valid CKINn with the highest priority (1 being the highest priority) is automatically selected.
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Si53xx-RM 6.4. Digital Hold/VCO Freeze All Any-Frequency Precision Clock devices feature a hold over or VCO freeze mode, whereby the DSPLL is locked to a digital value. 6.4.1. Narrowband Digital Hold (Si5316, Si5323, Si5366) If an LOS or FOS condition exists on the selected input clock, the device enters digital hold. In this mode, the device provides a stable output frequency until the input clock returns and is validated.
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Si53xx-RM 6.6. Output Phase Adjust (Si5323, Si5366) Overall device skew (CKINn to CKOUT_n phase delay) is controllable via the INC and DEC input pins. A positive pulse applied at the INC pin increases the device skew by 1/fOSC, one period of the DCO output clock. A pulse on the DEC pin decreases the skew by the same amount. Since fOSC is close to 5 GHz, the resolution of the skew control is approximately 200 ps. Using the INC and DEC pins, there is no limit to the range of skew adjustment that can be made.
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Si53xx-RM 6.6.5. Disabling FS_OUT (Si5366) The FS_OUT maybe disabled via the DBLFS pin, see Table 29. The additional state (M) provided allows for FS_OUT to drive a CMOS load while the other clock outputs use a different signal format as specified by the SFOUT[1:0] pins. Table 29. FS_OUT Disable Control (DBLFS) DBLFS FS_OUT State H Tri-State/Powerdown M Active/CMOS Format L Active/SFOUT[1:0] Format 6.7.
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Si53xx-RM 6.8. PLL Bypass Mode The device supports a PLL bypass mode in which the selected input clock is fed directly to all enabled output buffers, bypassing the DSPLL. In PLL bypass mode, the input and output clocks will be at the same frequency. PLL bypass mode is useful in a laboratory environment to measure system performance with and without the effects of jitter attenuation provided by the DSPLL. The DSBL2/BYPASS pin is used to select the PLL bypass mode according to Table 31. Table 31.
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Si53xx-RM Table 32. Frequency Offset Control (FOS_CTL) FOS_CNTL Meaning L FOS Disabled. M Stratum 3/3E FOS Threshold (12 ppm) H SONET Minimum Clock Threshold (48 ppm) 6.9.3. FSYNC Align Alarm (Si5366 and CK_CONF = 1 and FRQTBL = L) At power-up or any time after the PLL has lost lock and relocked, the device automatically performs a realignment of FS_OUT using the currently active sync input.
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Si53xx-RM 6.9.5.1. PLL Lock Detect (Si5316, Si5323, Si5366) The PLL lock detection algorithm indicates the lock status on the LOL output pin. The algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. If the time between two consecutive phase cycle slips is greater than the Retrigger Time, the PLL is in lock. The LOL output has a guaranteed minimum pulse width as shown in (Table 8, “AC Characteristics—All Devices”).
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Si53xx-RM 7. Microprocessor Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375) The devices in this family provide a rich set of clock multiplication/clock division options, loop bandwidth selections, output clock phase adjustment, and device control options. 7.1. Clock Multiplication The input frequency, clock multiplication ratio, and output frequency are set via register settings.
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Si53xx-RM Because there is only one DCO and all of the outputs must be frequencies that are integer divisions of the DCO frequency, there are restrictions on the ratio of one output frequency to another output frequency. That is, there is considerable freedom in the ratio between the input frequency and the first output frequency; but once the first output frequency is chosen, there are restrictions on subsequent output frequencies.
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Si53xx-RM Xtal, or Refclock (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369; Refclock only for the Si5374 and Si5375) BYPASS 2 CKIN_1+ CKIN_1– 2 CKIN_2+ CKIN_2– ÷ N31 ÷ N32 f3 Si5368 Si5369 f3 2 CKIN_3+ CKIN_3– 2 CKIN_4+ CKIN_4– ÷ NC1 fx Digital Phase M Detector/ Loop Filter DCO fOSC ÷ N33 ÷ N2_LS ÷ N34 ÷ N1_HS ÷ NC2 Si5368 Si5369 ÷ NC3 ÷ NC5 Control Bandwidth Control 2 CKOUT_1+ CKOUT_1– 2 CKOUT_2+ CKOUT_2– 2 CKOUT_3+ CKOUT_3– 2 CKOUT_4+ CKOUT_4– 2 CKOUT_5+ CKOUT_5– 0 1 0
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Si53xx-RM The output divider, NC1, is the product of a high-speed divider (N1_HS) and a low-speed divider (N1_LS). Similarly, the feedback divider N2 is the product of a high-speed divider N2_HS and a low-speed divider N2_LS. When multiple combinations of high-speed and low-speed divider values are available to produce the desired overall result, selecting the largest possible high-speed divider value will produce lower power consumption.
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Si53xx-RM calibration and will appear after the self-calibration routine is completed. The SQ_ICAL bit is self-clearing after a successful ICAL. After a successful self-calibration has been performed with a valid input clock, it is not necessary to reinitiate a selfcalibration for subsequent losses of input clock. If the input clock is lost following self-calibration, the device enters digital hold mode.
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Si53xx-RM 7.3. Input Clock Configurations (Si5367 and Si5368) The device supports two input clock configurations based on CK_CONFIG_REG. See "6.5. Frame Synchronization (Si5366)" on page 70 for additional details. 7.4. Input Clock Control This section describes the clock selection capabilities (manual input selection, automatic input selection, hitless switching, and revertive switching). The Si5319, Si5327, and Si5375 support only pin-controlled manual clock selection.
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Si53xx-RM CKIN1 CKIN2 Selected Clock CKIN3 CKIN4 LOS/FOS detect LOS/FOS detect LOS/FOS detect LOS/FOS detect 8 CK_PRIORn Clock priority logic 2 1 2 2 2 CKSEL_REG CS0_C3A, CS1_C4A pins 0 Auto 2 AUTOSEL_REG decode 0 2 Manual 1 CKSEL_PIN Figure 28. Si5367, Si5368, and Si5369 Input Clock Selection 7.4.1. Manual Clock Selection (Si5324, Si5325, Si5326, Si5367, Si5368, Si5369, Si5374) Manual control of input clock selection is available by setting the AUTOSEL_REG[1:0] register bits to 00.
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Si53xx-RM Table 39. Manual Input Clock Selection (Si5324, Si5325, Si5326, Si5374) CKSEL_REG or CS pin Active Input Clock 0 CKIN1 1 CKIN2 If the selected clock enters an alarm condition, the PLL enters digital hold mode. The CKSEL_REG[1:0] controls are ignored if automatic clock selection is enabled. 7.4.2. Automatic Clock Selection (Si5324, Si5325, Si5326, Si5367, Si5368, Si5369, Si5374) The AUTOSEL_REG[1:0] register bits sets the input clock selection mode as shown in Table 40.
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Si53xx-RM 7.4.2.2. Detailed Automatic Clock Selection Description (Si5367, Si5368, Si5369) The prioritization of clock inputs for automatic switching is shown in Table 41. For example, if CK_CONFIG_REG = 0 and the desired clock priority order is CKIN4, CKIN3, CKIN2, and then CKIN1 as the lowest priority clock, the user should set CK_PRIOR1[1:0] = 11, CK_PRIOR2[1:0] = 10, CK_PRIOR3[1:0] = 01, and CK_PRIOR4[1:0] = 00. Table 41.
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Si53xx-RM 7.5. Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374 and Si5375 Free Run Mode Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375 C K IN 1 C K IN 2 C rystal or an external oscillator (external oscillator only for the Si5374/75) XB XA Xtal osc  N 31  N 32 XA-X B D SPLL C ore C K O U T1 C K O U T2 C ontrol I 2 C/SPI Figure 29. Free Run Mode Block Diagram       CKIN2 has an extra mux with a path to the crystal oscillator output.
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Si53xx-RM 7.5.3. Free Run Reference Frequency Constraints XA/XB Frequency Min XA/XB Frequency Max Xtal 109 MHz 125.
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Si53xx-RM 7.6. Digital Hold All Any-Frequency Precision Clock devices feature a holdover mode, whereby the DSPLL is locked to a digital value. 7.6.1. Narrowband Digital Hold (Si5316, Si5324, Si5326, Si5368, Si5369, Si5374) After the part's initial self-calibration (ICAL), when no valid input clock is available, the device enters digital hold.
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Si53xx-RM Table 42. Digital Hold History Delay HIST_DEL[4:0] History Delay Time (ms) HIST_DEL[4:0] History Delay Time (ms) 00000 0.0001 10000 6.55 00001 0.0002 10001 13 00010 0.0004 10010 (default) 26 00011 0.0008 10011 52 00100 0.0016 10100 105 00101 0.0032 10101 210 00110 0.0064 10110 419 00111 0.01 10111 839 01000 0.03 11000 1678 01001 0.05 11001 3355 01010 0.10 11010 6711 01011 0.20 11011 13422 01100 0.41 11100 26844 01101 0.
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Si53xx-RM 7.6.2. History Settings for Low Bandwidth Devices (Si5324, Si5327, Si5369, Si5374) Because of the extraordinarily low loop bandwidth of the Si5324, Si5369 and Si5374, it is recommended that the values for both history registers be increased for longer histories. 7.6.3. Recovery from Digital Hold (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374) When the input clock signal returns, the device transitions from digital hold to the selected input clock.
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Si53xx-RM 7.7. Output Phase Adjust (Si5326, Si5368) The device has a highly accurate, digitally controlled device skew capability. For more information on Output Phase Adjustments, see both DSPLLsim and the respective data sheets. Both can be downloaded by going to www.silabs.com/timing and clicking on “Documentation” at the bottom of the page. 7.7.1.
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Si53xx-RM Before writing a new FLAT[14:0] value, the FLAT_VALID bit must be set to 0 to hold the existing FLAT[14:0] value while the new value is being written. Once the new value is written, set FLAT_VALID = 1 to enable its use. To verify a written value into FLAT, the FLAT register should be read after the register is written. Because the FLAT resolution varies with the frequency plan and selected bandwidth, DSPLLsim reports the FLAT resolution each time it creates a new frequency plan. 7.7.2.1.
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Si53xx-RM Table 44. CKIN3/CKIN4 Frequency Selection (CK_CONF = 1) CKLNnRATE[2:0] CKINn Frequency (kHz) Divisor 000 2–4 1 001 4–8 2 010 8–16 4 011 16–32 8 100 32–64 16 101 64–128 32 110 128–256 64 111 256–512 128 DCO,  N1_HS 4.85 GHz to 5.67 GHz  NC2_LS CKOUT2  NC5_LS CKIN3  CLKIN3RATE to align CKIN4  CLKIN4RATE Typically the same frequency Clock select Figure 32. Frame Sync Frequencies 92 Rev. 0.
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Si53xx-RM The NC5_LS divider uses CKOUT2 as its clock input to derive FS_OUT. The limits for the NC5_LS divider are NC5_LS = [1, 2, 4, 6, …, 219] fCKOUT2 < 710 MHz Note that when in frame synchronization realignment mode, writes to NC5_LS are controlled by FPW_VALID. See section “7.8.4. FS_OUT Polarity and Pulse Width Control (Si5368)”. Common NC5_LS divider settings on FS_OUT are shown in Table 45. Table 45.
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Si53xx-RM For cases where phase skew is required, see Section “7.7. Output Phase Adjust (Si5326, Si5368)” for more details on controlling the sync input to sync output phase skew via the FSYNC_SKEW[16:0] bits. See Section “8.2. Output Clock Drivers” for information on the FS_OUT signal format, pulse width, and active logic level control. 7.8.2.
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Si53xx-RM 7.9. Output Clock Drivers (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375) The device includes a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS, CML, and CMOS formats. The signal format of each output is individually configurable through the SFOUTn_REG[2:0] register bits, which modify the output common mode and differential signal swing.
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Si53xx-RM 7.10. PLL Bypass Mode (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375) The device supports a PLL bypass mode in which the selected input clock is fed directly to the output buffers, bypassing the DSPLL. In PLL bypass mode, the input and output clocks will be at the same frequency. PLL bypass mode is useful in a laboratory environment to measure system performance with and without the jitter attenuation provided by the DSPLL.
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Si53xx-RM 7.11.1.2. Standard LOS (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375) To facilitate automatic hitless switching, the LOS trigger time can be significantly reduced by using the default LOS option (LOSn_EN = 11). The LOS circuitry divides down each input clock to produce a 2 kHz to 2 MHz signal. The LOS circuitry over samples this divided down input clock using a 40 MHz clock to search for extended periods of time without input clock transitions.
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Si53xx-RM Table 50. FOS Reference Clock Selection FOS Reference FOSREFSEL[2:0] Si5326 Si5368 000 XA/XB XA/XB 001 CKIN1 CKIN1 010 CKIN2 (default) CKIN2 (default) 011 Reserved CKIN3 100 Reserved CKIN4 all others Reserved Reserved Both the FOS reference and the FOS monitored clock must be divided down to the same clock rate and this clock rate must be between 10 MHz and 27 MHz.
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Si53xx-RM 7.11.3. C1B, C2B (Si5319, Si5324, Si5325, Si5326, Si5327, Si5374, Si5375) A LOS condition causes the associated LOS1_INT or LOS2_INT read only register bit to be set. A LOS condition on CKIN_1 will also be reflected onto C1B if CK1_BAD_PIN = 1. Likewise, a LOS condition on CKIN_2 will also be reflected onto C2B if CK2_BAD_PIN = 1. A FOS condition causes the associated FOS1_INT or FOS2_INT read only register bit to be set. FOS monitoring is enabled or disabled using the FOS_EN bit.
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Si53xx-RM 7.11.6. C1B, C2B, C3B, ALRMOUT (Si5368 [CK_CONFIG_REG = 1]) The generation of alarms on the C1B, C2B, C3B, and ALRMOUT outputs is a function of the input clock configuration, and the frequency offset alarm enable as shown in Table 53. The LOSn_INT and FOSn_INT signals are the raw outputs of the alarm monitors. These appear directly in the device status registers. Sticky versions of these bits (LOSn_FLG, FOSn_FLG) drive the output interrupt and can be individually masked.
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Si53xx-RM Table 54. Lock Detect Retrigger Time (LOCKT) LOCKT[2:0] Retrigger Time (ms) 000 106 001 53 010 26.5 011 13.3 100 6.6 (value after reset) 101 3.3 110 1.66 111 .833 7.11.9. Device Interrupts Alarms on internal real-time status bits such as LOS1_INT, FOS1_INT, etc. cause their associated interrupt flags (LOS1_FLG, FOS1_FLG, etc.) to be set and held. The interrupt flag bits can be individually masked or unmasked with respect to the output interrupt pin.
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Si53xx-RM 7.13. I2C Serial Microprocessor Interface When configured in I2C control mode (CMODE = L), the control interface to the device is a 2-wire bus for bidirectional communication. The bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL). Both lines must be connected to the positive supply via an external pull-up. In addition, an output interrupt (INT) is provided with selectable active polarity (determined by INT_POL bit).
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Si53xx-RM 7.14. Serial Microprocessor Interface (SPI) When configured in SPI control mode (CMODE = H), the control interface to the device is a 4-wire interface modeled after commonly available microcontroller and serial peripheral devices. The interface consists of a clock input (SCLK), slave select input (SSb), serial data input (SDI), and serial data output (SDO). In addition, an output interrupt (INT) is provided with selectable active polarity (determined by INT_POL bit).
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Si53xx-RM SS SCLK SDI 7 6 5 4 3 2 1 0 7 6 Instruction Byte SDO 5 4 3 2 1 0 Address or Write Data High Impedance Figure 36. SPI Write/Set Address Command SS SCLK SDI 7 6 5 4 3 2 1 0 Read Command SDO 7 High Impedance 6 5 4 3 2 1 0 Read Data Figure 37. SPI Read Command 7.14.1.
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Si53xx-RM 8. High-Speed I/O 8.1. Input Clock Buffers Any-Frequency Precision Clock devices provide differential inputs for the CKINn clock inputs. These inputs are internally biased to a common mode voltage and can be driven by either a single-ended or differential source. Figure 38 through Figure 41 show typical interface circuits for LVPECL, CML, LVDS, or CMOS input clocks. Note that the jitter generation improves for higher levels on CKINn (within the limits in Table 8, “AC Characteristics—All Devices”).
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Si53xx-RM Si53xx C CKIN + CML/ LVDS Driver 40 k 300  100  ± 40 k VICM CKIN _ C Figure 40. CML/LVDS Termination (1.8, 2.5, 3.3 V) CMOS Driver V DD V DD V DD Si53xx R3 R1 R2 C1 CKIN+ See Table 33 ohms R4 150 ohms VDD R2 Notes 3.3 V 2.5 V 1.8 V 100 ohm 49.9 ohm 14.7 ohm Locate R1 near CMOS driver Locate other components near Si5317 Recalculate resistor values for other drive strengths CKIN– C2 100 nF Figure 41. CMOS Termination (1.8, 2.5, 3.3 V) Rev. 0.
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Si53xx-RM 8.2. Output Clock Drivers The output clocks can be configured to be compatible with LVPECL, CML, LVDS, or CMOS as shown in Table 56. Unused outputs can be left unconnected. For microprocessor-controlled devices, it is recommended to write “disable” to SFOUTn to disable the output buffer and reduce power. When the output mode is CMOS, bypass mode is not supported. Table 56.
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Si53xx-RM Si53xx 10  80  10  All resistors are located next to RCVR Rcvr Figure 43. Differential Output Example Requiring Attenuation Si53xx CMOS Logic CKOUTn Optionally Tie CKOUTn Outputs Together for Greater Strength Figure 44. Typical CMOS Output Circuit (Tie CKOUTn+ and CKOUTn– Together) Unused output drivers should be powered down, per Table 57, or left floating. The pin-controlled parts have a DBL2_BY pin that can be used to disable CKOUT2. Table 57.
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Si53xx-RM + Output Disable 100  100  CKOUT+ CKOUT - Figure 45. CKOUT Structure 8.2.3. Typical Clock Output Scope Shots Table 58. Output Format Measurements1,2 Name SFOUT Pin SFOUT Code Single Vpk–pk Diff Vpk–pk Vocm Reserved HH — — — — LVDS HM 7 .35 .7 1.2 CML HLK 6 .25 .5 3.05 LVPECL MH 5 .75 1.5 2.10 Reserved MM 4 — — — Low Swing LVDS ML 3 .25 .5 1.2 CMOS LH 2 3.3 — 1.65 Disable LM 1 — — — Reserved LL 0 — — — Notes: 1.
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Si53xx-RM 8.3. Typical Scope Shots for SFOUT Options Figure 46. sfout_2, CMOS Figure 47. sfout_3, lowSwingLVDS 110 Rev. 0.
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Si53xx-RM Figure 48. sfout_5, LVPECL Figure 49. sfout_6, CML Rev. 0.
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Si53xx-RM Figure 50. sfout_7, LVDS 112 Rev. 0.
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Si53xx-RM 8.4. Crystal/Reference Clock Interfaces (Si5316, Si5319, Si5323, Si5324, Si5326, Si5327, Si5366, Si5368, Si5369, Si5374, and Si5375) All devices other than the Si5374 and Si5375 can use an external crystal or external clock as a reference. The Si5374 and Si5375 are limited to an external reference oscillator and cannot use a crystal. If an external clock is used, it must be ac coupled. With appropriate buffers, the same external reference clock can be applied to CKINn.
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Si53xx-RM 0.01 F Si53xx 1.2 V XA 100  LVDS, LVPECL, CML, etc. 0.01 F XB 10 k 10 k 0.6 V Figure 53. Differential External Reference Input Example (Not for Si5374 or Si5375) 0.01 F LVDS, LVPECL, CML, etc. 0.01 F Si5374/75 OSC-P OSC-N 100  1.2 V 2.5 k 0.6 V Figure 54. Differential OSC Reference Input Example for Si5374 and Si5375 114 Rev. 0.
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Si53xx-RM 8.5. Three-Level (3L) Input Pins (No External Resistors) Si53xx VDD 75 k Iimm 75 k External Driver Figure 55. Three Level Input Pins Parameter Symbol Min Max Input Voltage Low Vill — .15 x VDD Input Voltage Mid Vimm .45 x Vdd .55 x VDD Input Voltage High Vihh .
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Si53xx-RM 8.6. Three-Level (3L) Input Pins (With External Resistors) V DD Iimm External Driver V DD Si53xx 18 k 75 k 18 k 75 k One of eight resistors from a Panasonic EXB-D10C183J (or similar) resistor pack Figure 56. Three Level Input Pins Parameter Symbol Min Max Input Low Current Iill –30 µA — Input Mid Current Iimm –11 µA –11 µA Input High Current Iihh — –30 µA Note: The above currents are the amount of leakage that the 3L inputs can tolerate from an external driver.
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Si53xx-RM 9. Power Supply These devices incorporate an on-chip voltage regulator to power the device from supply voltages of 1.8, 2.5, or 3.3 V. Internal core circuitry is driven from the output of this regulator while I/O circuitry uses the external supply voltage directly. Figure 57 shows a typical power supply bypass network for the TQFP packages. Figure 58 shows a typical power supply bypass network for QFN.
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Si53xx-RM 10. Packages and Ordering Guide Refer to the respective data sheet for your device packaging and ordering information. 118 Rev. 0.
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Si53xx-RM APPENDIX A—NARROWBAND REFERENCES Resonator/External Clock Selection Table 59 shows the 114.285 MHz third overtone crystals that have been approved for use with the Si53xx jitter attenuating clocks. Table 59. Approved Crystals Manufacturer Part Number Web Site Stability Initial Accuracy TXC 7MA1400014 http://www.txc.com.tw 100 ppm 100 ppm Connor Winfield CS-018 http://www.conwin.com 100 ppm 100 ppm Connor Winfield CS-023 http://www.conwin.
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Si53xx-RM Fundamental Mode Crystals For cost sensitive applications that do not have the most demanding jitter requirements, all of the narrow band devices can use fundamental mode crystals that are in the lowest frequency band ranging from 37 to 41 MHz (corresponding to RATE = LL). Unlike the other narrowband members of the family, the Si5327 is only capable of using fundamental mode crystals that are in this range.
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Si53xx-RM APPENDIX B—FREQUENCY PLANS AND JITTER PERFORMANCE (Si5316, Si5319, Si5323, SI5324, Si5326, Si5327, Si5366, Si5368, Si5369, Si5374, Si5375) Introduction To achieve the best jitter performance from Narrowband Any-Frequency Clock devices, a few general guidelines should be observed: High f3 Value f3 is defined as the comparison frequency at the Phase Detector. It is equal to the input frequency divided by N3.
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Si53xx-RM Figure 61 shows similar results and ties them to RMS jitter values. It also helps to illustrate one potential remedy for solutions with low f3. Note that 38.88 MHz x 5 = 194.4 MHz. In this case, an FPGA was used to multiply a 38.88 MHz input clock up by a factor of five to 194.4 MHz, using a feature such as the Xilinx DCM (Digital Clock Manager).
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Si53xx-RM Reference vs. Output Frequency Because of internal coupling, output frequencies that are an integer multiple (or close to an integer multiple) of the XA/XB reference frequency (either internal or external) should be avoided. Figure 62 illustrates this by showing a 38.88 MHz reference being used to generate both a 622.08 MHz output (which is an integer multiple of 38.88 MHz) and 696.399 MHz (which is not an integer multiple of 38.88 MHz). Notice the mid-band spurs on the 622.
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Si53xx-RM High Reference Frequency When selecting a reference frequency, with all other things being equal, the higher the reference frequency, the lower the output jitter. Figures 63 and 64 illustrate this. For a discussion of the available reference frequencies, see section " Resonator/External Clock Selection" on page 119. 37 MHz thru 163 MHz Ext Ref, 155.52 MHz in, 622.
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Si53xx-RM 41 MHz thru 180 MHz Ext Ref, 155.52 MHz in, 622.08 MHz out 0 Phase Noise (dBc/Hz) -20 -40 -60 -80 -100 -120 -140 -160 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Dark Blue—41 MHz Light Blue—61 MHz Red—125.5 MHz Green—180 MHz Figure 64. Jitter vs. Reference Frequency (2 of 2) All phase noise numbers are in fs, RMS External Reference Frequency: 37 41 55 61 109 125.
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Si53xx-RM APPENDIX C—TYPICAL PHASE NOISE PLOTS Introduction The following are some typical phase noise plots. The clock input source is a Rohde and Schwarz model SML03 RF Generator. Except as noted, the phase noise analysis equipment is the Agilent E5052B. Also (except as noted), the Any-Frequency part was an Si5326 operating at 3.3 V with an ac-coupled differential PECL output and an accoupled differential sine wave input from the RF generator at 0 dBm.
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Si53xx-RM Figure 66. 155.52 MHz In; 622.08 MHz Out; Loop BW = 7 Hz, Si5324 Rev. 0.
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Si53xx-RM Figure 67. 19.44 MHz In; 156.25 MHz Out; Loop BW = 80 Hz 128 Rev. 0.
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Si53xx-RM Figure 68. 19.44 MHz In; 156.25 MHz Out; Loop BW = 5 Hz, Si5324 Rev. 0.
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Si53xx-RM Figure 69. 27 MHz In; 148.35 MHz Out; Light Trace BW = 6 Hz; Dark Trace BW = 110 Hz, Si5324 130 Rev. 0.
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Si53xx-RM Figure 70. 61.44 MHz In; 491.52 MHz Out; Loop BW = 7 Hz, Si5324 Rev. 0.
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Si53xx-RM Figure 71. 622.08 MHz In; 672.16 MHz Out; Loop BW = 6.9 kHz 132 Rev. 0.
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Si53xx-RM Figure 72. 622.08 MHz In; 672.16 MHz Out; Loop BW = 100 Hz Rev. 0.
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Si53xx-RM Figure 73. 156.25 MHz In; 155.52 MHz Out 134 Rev. 0.
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Si53xx-RM Figure 74. 78.125 MHz In; 644.531 MHz Out Table 63. Jitter Values for Figure 74 Jitter Bandwidth 644.531 MHz Jitter (RMS) Broadband, 1 kHz to 10 MHz 223 fs OC-48, 12 kHz to 20 MHz 246 fs OC-192, 20 kHz to 80 MHz 244 fs OC-192, 4 MHz to 80 MHz 120 fs OC-192, 50 kHz to 80 MHz 234 fs Broadband, 800 Hz to 80 MHz 248 fs Rev. 0.
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Si53xx-RM Figure 75. 78.125 MHz In; 690.569 MHz Out Table 64. Jitter Values for Figure 75 136 Jitter Bandwidth 690.569 MHz Jitter (RMS) Broadband, 1 kHz to 10 MHz 244 fs OC-48, 12 kHz to 20 MHz 260 fs OC-192, 20 kHz to 80 MHz 261 fs OC-192, 4 MHz to 80 MHz 120 fs OC-192, 50 kHz to 80 MHz 253 fs Broadband, 800 Hz to 80 MHz 266 fs Rev. 0.
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Si53xx-RM Figure 76. 78.125 MHz In; 693.493 MHz Out Table 65. Jitter Values for Figure 76 Jitter Bandwidth 693.493 MHz Jitter (RMS) Broadband, 1 kHz to 10 MHz 243 fs OC-48, 12 kHz to 20 MHz 265 fs OC-192, 20 kHz to 80 MHz 264 fs OC-192, 4 MHz to 80 MHz 124 fs OC-192, 50 kHz to 80 MHz 255 fs Broadband, 800 Hz to 80 MHz 269 fs Rev. 0.
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Si53xx-RM 86.685 MHz in, 173.371 MHz and 693.493 MHz out 0.00E+00 Phase Noise (dBc/Hz) -2.00E+01 -4.00E+01 -6.00E+01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.60E+02 -1.80E+02 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08 Offset Frequency (Hz) Red = 693.493 MHz Blue = 173.371 MHz Figure 77. 86.685 MHz In; 173.371 MHz and 693.493 MHz Out Table 66. Jitter Values for Figure 77 138 Jitter Bandwidth 173.371 MHz Jitter (RMS) 693.
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Si53xx-RM Figure 78. 86.685 MHz In; 173.371 MHz Out Rev. 0.
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Si53xx-RM Figure 79. 86.685 MHz In; 693.493 MHz Out 140 Rev. 0.
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Si53xx-RM 155.52 MHz and 156.25MHz in, 622.08 MHz out 0.00E+00 Pha ase Noise (dB Bc/Hz) -2.00E+01 -4.00E+01 -6.00E+01 6.00E 01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.60E+02 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08 Offset Frequency (Hz) Blue = 155.52 MHz Red = 156.25 MHz Figure 80. 155.52 MHz and 156.25 MHz In; 622.08 MHz Out Table 67. Jitter Values for Figure 80 Jitter Bandwidth 155.52 MHz Input Jitter (RMS) 156.
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Si53xx-RM Figure 81. 10 MHz In; 1 GHz Out 142 Rev. 0.
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Si53xx-RM Digital Video (HD-SDI) 27 MHz in, 148.5 MHz out 0 Phase Noise (dBc/Hz) -20 -40 -60 -80 -100 -120 -140 -160 10 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Jitter Band Brick Wall, 10 Hz to 20 MHz Peak-to-peak Jitter 2.42 ps, RMS 14.0 ps Phase noise equipment: Agilent model JS500. Rev. 0.
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Si53xx-RM APPENDIX D—ALARM STRUCTURE LOS_INT in Sticky LOSX_FLG out LOSX_MSK Write 0 to clear INT_POL LOS1_INT in Sticky LOS1_FLG out LOS1_MSK Write 0 to clear LOS2_INT in Sticky LOS2_FLG out LOS2_MSK Write 0 to clear FOS1_INT in Sticky FOS1_FLG out FOS1_MSK Write 0 to clear FOS2_INT in Sticky FOS2_FLG out FOS2_MSK Write 0 to clear LOL_INT in Sticky LOL_FLG out LOL_MSK Write 0 to clear WIDEBAND MODE LOS1-EN CKIN1 LOS1_INT LOS Detector CK_BAD_POL PD_CK1 INT_C1B
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Si53xx-RM LOS_INT in Sticky out Write 0 to clear LOS1_INT in in Sticky out Sticky out Write 0 to clear LOS3_INT in Sticky out Write 0 to clear LOS4_INT in Sticky out Write 0 to clear FOS1_INT in Sticky out Write 0 to clear FOS2_INT in Sticky out Write 0 to clear FOS3_INT in Sticky out Write 0 to clear FOS4_INT in Sticky out Write 0 to clear ALIGN_INT in Sticky out Write 0 to clear LOL_INT in LOSX_MSK INT_POL Write 0 to clear LOS2_INT LOSX_FLG Sticky out Write 0 to clear
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Si53xx-RM LOS3_EN CKIN3 LOS3_INT LOS Detector CK_BAD_POL PD_CK3 C3B FOS Detector E FOS3_EN LOSI_EN CKIN1 LOS1_INT LOS Detector CK3_BAD_PIN CK_CONFIG_REG FOS_EN PD_CK1 C1B 1 E FOS Detector 0 FOS_EN CK1_BAD_PIN FOSI_EN CK_CONFIG_REG FSYNC_SWTCH_REG LOS2_EN LOS4_INT CKIN2 LOS Detector LOS2_INT PD_CK2 C2B 1 E FOS Detector 0 CK2_BAD_PIN FOS2_EN FOS_EN Figure 84. Si5368 Alarm Diagram (2 of 2) 146 Rev. 0.
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Si53xx-RM APPENDIX E—INTERNAL PULLUP, PULLDOWN BY PIN Tables 68–79 show which 2-Level CMOS pins have pullups or pulldowns. Note the value of the pullup/pulldown resistor is typically 75 k. Table 68. Si5316 Pullup/Down Pin # Si5316 Pull? 1 RST U 11 RATE0 U, D 14 DBL2_BY U, D 15 RATE1 U, D 21 CS U, D 22 BWSEL0 U, D 23 BWSEL1 U, D 24 FRQSEL0 U, D 25 FRQSEL1 U, D 26 CK1DIV U, D 27 CK2DIV U, D 30 SFOUT1 U, D 33 SFOUT0 U, D Table 69.
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Si53xx-RM Table 70. Si5323 Pullup/Down Pin # Si5323 Pull? 1 RST U 2 FRQTBL U, D 9 AUTOSEL U, D 11 RATE0 U, D 14 DBL2_BY U, D 15 RATE1 U, D 19 DEC D 20 INC D 21 CS_CA U, D 22 BWSEL0 U, D 23 BWSEL1 U, D 24 FRQSEL0 U, D 25 FRQSEL1 U, D 26 FRQSEL2 U, D 27 FRQSEL3 U, D 30 SFOUT1 U, D 33 SFOUT0 U, D Table 71.
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Si53xx-RM Table 72. Si5325 Pullup/Down Pin # Si5325 Pull? 1 RST U 21 CS_CA U, D 22 SCL D 24 A0 D 25 A1 D 26 A2_SS D 27 SDI D 36 CMODE U, D Table 73. Si5326 Pullup/Down Pin # Si5326 Pull? 1 RST U 11 RATE0 U, D 15 RATE1 U, D 19 DEC D 20 INC D 21 CS_CA U, D 22 SCL D 24 A0 D 25 A1 D 26 A2_SS D 27 SDI D 36 CMODE U, D Rev. 0.
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Si53xx-RM Table 74. Si5327 Pullup/Down Pin # Si5327 Pull? 1 RST U 11 RATE0 U, D 15 RATE1 U, D 21 CS U, D 22 SCL D 24 A0 D 25 A1 D 26 A2_SS D 27 SDI D 36 CMODE U, D Table 75.
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Si53xx-RM Table 76. Si5366 Pullup/Down Pin # Si5366 Pull? 3 RST U 4 FRQTBL U, D 13 CS0_C3A D 20 FS_SW D 21 FS_ALIGN D 22 AUTOSEL U, D 32 RATE0 U, D 37 DBL2_BY U, D 42 RATE1 U, D 50 DBL_FS U, D 51 CK_CONF D 54 DEC D 55 INC D 56 FOS_CTL U, D 57 CS1_C4A U, D 60 BWSEL0 U, D 61 BWSEL1 U, D 66 DIV34_0 U, D 67 DIV34_1 U, D 68 FRQSEL0 U, D 69 FRQSEL1 U, D 70 FRQSEL2 U, D 71 FRQSEL3 U, D 80 SFOUT1 U, D 85 DSBL34 U 95 SFOUT0 U, D Rev. 0.
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Si53xx-RM Table 77. Si5367 Pullup/Down Pin # Si5367 Pull? 3 RST U 13 CS0_C3A D 57 CS1_C4A U, D 60 SCL D 68 A0 D 69 A1 D 70 A2_SSB D 71 SDI D 90 CMODE U, D Table 78. Si5368 Pullup/Down 152 Pin # Si5368 Pull? 3 RST U 13 CS0_C3A D 21 FS_ALIGN D 32 RATE0 U, D 42 RATE1 U, D 54 DEC D 55 INC D 57 CS1_C4A U, D 60 SCL D 68 A0 D 69 A1 D 70 A2_SSB D 71 SDI D 90 CMODE U, D Rev. 0.
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Si53xx-RM Table 79. Si5369 Pullup/Down Pin # Si5368 Pull? 3 RST U 13 CS0_C3A D 21 FS_ALIGN D 32 RATE0 U, D 42 RATE1 U, D 57 CS1_C4A U, D 60 SCL D 68 A0 D 69 A1 D 70 A2_SSB D 71 SDI D 90 CMODE U, D Table 80. Si5374/75 Pullup/Down Pin # Si5374/75 Pull? D4 RSTL_A U D6 RSTL_B U F6 RSTL_C U F4 RSTL_D U D1 CS_CA_A U/D A6 CS_CA_B U/D F9 CS_CA_C U/D J4 CS_CA_A U/D G5 SCL D Rev. 0.
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Si53xx-RM APPENDIX F—TYPICAL PERFORMANCE: CROSSTALK, OUTPUT FORMAT JITTER BYPASS MODE, PSRR, This appendix is divided into the following four sections:  Bypass Mode Performance Power Supply Noise Rejection  Crosstalk  Output Format Jitter  Bypass: 622.08 MHz In, 622.08 MHz Out 622.08 M Hz in, 622.
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Si53xx-RM Power Supply Noise Rejection Power Supply Noise to Output Transfer Function -60 -65 -70 dB -75 -80 -85 -90 -95 -100 -105 1 10 100 1000 kHz 38.88 MHz in, 155.52 MHz out; Bandwidth = 110 Hz Rev. 0.
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Si53xx-RM Clock Input Crosstalk Results: Test Conditions Jitter Band 155.52 MHz in, 155.521 MHz in, 155.521 MHz in, 155.521 MHz in, 155.521 MHz in, 622 MHz out, 622.084 MHz 622.084 MHz 622.084 MHz 622.084 MHz For reference, out, out, out, out, No crosstalk No crosstalk 155.52 MHz 155.52 MHz 155.52 MHz Xtalk, Xtalk, Xtalk, 99 Hz loop 6.
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Si53xx-RM Clock Input Crosstalk: Phase Noise Plots 1 5 5 . 5 2 1 M H z in , 6 2 2 .0 8 4 M H z o u t 0 -2 0 Phase Noise (dBc/Hz) -4 0 -6 0 -8 0 -10 0 -12 0 -14 0 -16 0 -18 0 1 00 1000 10000 100000 1000000 1 0 0 00 0 0 0 1 0 0 00 0 0 00 O f f s e t F r e q u e n c y (H z ) Dark blue — No crosstalk Light blue — With crosstalk, low bandwidth Yellow — With crosstalk, high bandwidth Red — With crosstalk, in digital hold Rev. 0.
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Si53xx-RM Clock Input Crosstalk: Detail View 155 .521 MH z i n, 622 .084 MH z ou t -60 Phase Noise (dBc/Hz) -70 -80 -90 -100 -110 -120 -130 100 1000 10000 O ffset F req u ency ( Hz) Dark blue — No crosstalk Light blue — With crosstalk, low bandwidth Yellow — With crosstalk, high bandwidth Red — With crosstalk, in digital hold 158 Rev. 0.
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Si53xx-RM Clock Input Crosstalk: Wideband Comparison 155 .521 M H z in , 62 2.08 4 M H z o u t 0 P h ase N oi se (d B c/ -20 -40 -60 -80 -100 -120 -140 -160 -180 100 1000 10000 100000 1000000 10000000 100000000 O ffse t Fre qu e ncy (H z ) Dark blue — Bandwidth = 6.72 kHz; no Xtalk Light blue — Bandwidth = 6.
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Si53xx-RM Clock Input Crosstalk: Output of Rohde and Schwartz RF R ohde and S chwarz : 155.521 M H z -60 P h ase Noi se (d Bc/ H -70 -80 -90 -100 -110 -120 100 1000 O ffse t Fre q ue n cy (Hz) 160 Rev. 0.
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Si53xx-RM Jitter vs. Output Format: 19.44 MHz In, 622.08 MHz Out 1 9.4 4 M H z in , 6 2 2.0 8 M H z o ut 0 -20 Phase Noise (dBc/Hz) -40 -60 -80 -1 00 -1 20 -1 40 -1 60 10 0 100 0 10000 1000 00 1 000 000 1000 000 0 10 00 0000 0 Offse t Fre quenc y (H z) Spectrum Analyzer: Agilent Model E444OA Table 81. Output Format vs.
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Si53xx-RM APPENDIX G—NEAR INTEGER RATIOS To provide more details and to provide boundaries with respect to the “Reference vs. Output Frequency” issue described in Appendix B on page 121, the following study was performed and is presented below. Test Conditions   XA/XB External Reference held constant at 38.88 MHz Input frequency centered at 155.52 MHz, then scanned.
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Si53xx-RM 38.88 MHz External XA-XB Reference 1200 RMS jitter, fs 1000 800 600 400 200 0 155.49 155.5 155.51 155.52 155.53 155.54 155.55 Input Frequency (MHz) Input Frequency Figure 86. ±200 ppm, 10 ppm Steps 38.88 MHz External XA-XB Reference 1200 RMS jitter, fs 1000 800 600 400 200 0 155.2 155.3 155.3 155.4 155.4 155.5 155.5 155.6 155.6 155.7 155.7 155.8 155.8 155.9 155.9 Input Frequency (MHz) Input Frequency Variation = ±2000 ppm Figure 87. ±2000 ppm, 50 ppm Steps Rev. 0.
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Si53xx-RM APPENDIX H—JITTER ATTENUATION AND LOOP BW The following illustrates the effects of different loop BW values on the jitter attenuation of the Any-Frequency devices. The jitter consists of sine wave modulation at varying frequencies. The RMS jitter values of the modulated sine wave input is compared to the output jitter of an Si5326 and an Si5324. For reference, the top entry in the table lists the jitter without any modulation.
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Si53xx-RM 622.08 MHz in, 622.08 MHz out 0.00E+00 Phase Noise (dBc/Hz) -2.00E+01 -4.00E+01 -6.00E+01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.60E+02 -1.80E+02 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08 Offset Frequency (Hz) Blue = RF Generator Green = Si5326 Red = Si5324 Figure 88. RF Generator, Si5326, Si5324; No Jitter (For Reference) 622.08 MHz in, 622.08 MHz out 0.00E+00 Phase Noise (dBc/Hz) -2.00E+01 -4.00E+01 -6.00E+01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.
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Si53xx-RM 622.08 MHz in, 622.08 MHz out 0.00E+00 Phase Noise (dBc/Hz) -2.00E+01 -4.00E+01 -6.00E+01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.60E+02 -1.80E+02 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08 Offset Frequency (Hz) Blue = RF Generator Green = Si5326 Red = Si5324 Figure 90. RF Generator, Si5326, Si5324 (100 Hz Jitter) 622.08 MHz in, 622.08 MHz out 0.00E+00 Phase Noise (dBc/Hz) -2.00E+01 -4.00E+01 -6.00E+01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.60E+02 -1.
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Si53xx-RM 622.08 MHz in, 622.08 MHz out 0.00E+00 Phase Noise (dBc/Hz) -2.00E+01 -4.00E+01 -6.00E+01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.60E+02 -1.80E+02 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08 Offset Frequency (Hz) Blue = RF Generator Green = Si5326 Red = Si5324 Figure 92. RF Generator, Si5326, Si5324 (1 kHz Jitter) 622.08 MHz in, 622.08 MHz out 0.00E+00 Phase Noise (dBc/Hz) -2.00E+01 -4.00E+01 -6.00E+01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.60E+02 -1.
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Si53xx-RM 622.08 MHz in, 622.08 MHz out 0.00E+00 Phase Noise (dBc/Hz) -2.00E+01 -4.00E+01 -6.00E+01 -8.00E+01 -1.00E+02 -1.20E+02 -1.40E+02 -1.60E+02 -1.80E+02 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 Offset Frequency (Hz) Blue = RF Generator Green = Si5326 Red = Si5324 Figure 94. RF Generator, Si5326, Si5324 (10 kHz Jitter) 168 Rev. 0.5 1.
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Si53xx-RM APPENDIX I—Si5374 AND Si5375 PCB LAYOUT RECOMMENDATIONS The following is a set of recommendations and guidelines for printed circuit board layout with the Si5374 and Si5374 devices. Because the four DSPLLs are in close physical and electrical proximity to one another, PCB layout is critical to achieving the highest levels of jitter performance. The following images were taken from the Si537xEVB (evaluation board) layout.
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Si53xx-RM These four resistors force the common RESET connection away from the BGA footprint Figure 96. Ground Plane and Reset 170 Rev. 0.
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Si53xx-RM The following is a set of recommendations and guidelines for printed circuit board layout with the Si5374 and Si5374 devices. Because the four DSPLLs are in close physical and electrical proximity to one another, PCB layout is critical to achieving the highest levels of jitter performance. The following images were taken from the Si537xEVB (evaluation board) layout. For more details about this board, please refer to the Si537x-EVB Evaluation Board User's Guide.
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Si53xx-RM OSC_P, OSC_N Avoid placing the OCS_P and OSC_N signals on the same layer as the clock outputs. Add grounded guard traces surrounding the OSC_P and OSC_N signals. Figure 98. OSC_P, OSC_N Routing 172 Rev. 0.
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Si53xx-RM APPENDIX J—Si5374 AND Si5375 CROSSTALK While the four DSPLLs of the Si5374 and Si5375 are in close physical and electrical proximity to one another, crosstalk interference between the DSPLLs is minimal. The following measurements show typical performance levels that can be expected for the Si5374 and Si5375 when all four of their DSPLLs are operating at frequencies that are close in value to one another, but not exactly the same.
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Si53xx-RM Figure 99. Si5374, Si5375 DSPLL A 174 Rev. 0.
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Si53xx-RM Figure 100. Si5374, Si5375 DSPLL B Rev. 0.
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Si53xx-RM Figure 101. Si5374, Si5375 DSPLL C 176 Rev. 0.
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Si53xx-RM Figure 102. Si5374, Si5375 DSPLL D Rev. 0.
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Si53xx-RM DOCUMENT CHANGE LIST Revision 0.3 to Revision 0.4        Updated AC Specifications in Table 8, “AC Characteristics—All Devices” Added Si5365, Si5366, Si5367, and Si5368 operation at 3.3 V Updated Section “7.8. Frame Synchronization Realignment (Si5368 and CK_CONFIG_REG = 1)” Added input clock control diagrams in Section “7.4.
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Si53xx-RM NOTES: Rev. 0.
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Si53xx-RM CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.