FMC XM104 Connectivity Card User Guide UG536 (v1.
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Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Support Resources . . . . . . . . . . . . . .
www.xilinx.com FMC XM104 Connectivity Card User Guide UG536 (v1.
Preface About This Guide This document describes the FPGA Mezzanine Card (FMC) XM104 connectivity card, referred to as the XM104 in this guide. Xilinx® supported evaluation (carrier) boards are referred to simply as boards in this guide. Guide Contents This manual contains the following chapter: • Chapter 1, XM104. Additional Documentation Prior to using the XM104, users should be familiar with Xilinx resources.
Preface: About This Guide 6 www.xilinx.com FMC XM104 Connectivity Card User Guide UG536 (v1.
Chapter 1 XM104 Overview This document describes the FPGA Mezzanine Card (FMC) XM104 connectivity module, referred to as the XM104 in this guide. A Quick Start section and Board Technical Description are combined within this document. Quick Start System Requirements Hardware Table 1-1 details the board validated to support the XM104. The ML605 board provides one FMC high pin count (HPC) (J64) and one FMC low pin count (LPC) (J63) connector interface.
Chapter 1: XM104 Software Example designs that use this hardware are not provided at this time.
Quick Start X-Ref Target - Figure 1-1 UG536_01_111609 Figure 1-1: Installation of XM104 to Board FMC HPC Connector Technical Support Xilinx offers technical support for this product only when used in conjunction with boards listed in Table 1-1. For assistance with the XM104 and Xilinx boards, contact Xilinx for technical support at www.xilinx.com/support. FMC XM104 Connectivity Card User Guide UG536 (v1.1) September 24, 2010 www.xilinx.
Chapter 1: XM104 Board Technical Description The XM104 provides a number of connectors which break out the FPGA multi-gigabit transceiver (MGT) interface signals to and from the board interface. Figure 1-2 shows a block diagram of the XM104. Each MGT data port interface consists of two differential pairs of MGT signals, one pair for the transmitter and one pair for the receiver. MGT Data Ports 0 and 1 are each wired to four SMA connectors.
Board Technical Description Detailed Description The numbered features in Figure 1-3 correlate to the features and notes listed in Table 1-2, page 12. For full functionality, the XM104 must be installed on a board FMC connector supporting high pin count interfaces. X-Ref Target - Figure 1-3 4 2 5 9 1 6 3 7 8 UG536_03_111609 Figure 1-3: FMC XM104 Connectivity Card User Guide UG536 (v1.1) September 24, 2010 www.xilinx.
Chapter 1: XM104 Table 1-2: XM104 Features Number Feature Notes Schematic Page 1 VITA 57.1 FMC HPC connector J1: Ten sets of FPGA multi-gigabit transceiver data port signals, a small number of FPGA single ended control signals from the board, clocks and power. The connector is mounted on the bottom side of the card. 2-5 2 MGT Data Port 0: Four SMA connectors FPGA multi-gigabit transceiver data port 0 on SMA connectors J3, J4, J5, J6.
Board Technical Description 1. VITA 57.1 FMC HPC Connector J1 This connector interfaces to the board containing the Xilinx FPGA and mating FMC connector. The XM104 uses Samtec FMC HPC connector part number ASP-134488-01. The XM104 connector mates with an FMC connector. See Xilinx board user guides and schematics for a description of features provided by HPC interfaces contained on the board, including power supply specifications, FPGA banking connectivity, and FPGA pin assignments.
Chapter 1: XM104 4. Multi-Gigabit Transceiver Data Port 2 - J11 SATA1 Board FPGA multi-gigabit transceiver Data Port 2 signals are wired to Serial ATA host connector J11 on the XM104. Data Port 2 connections between the XM104 FMC HPC connector and Serial ATA connector J11 are defined in Table 1-5.
Board Technical Description 6. Multi-Gigabit Transceiver Data Ports [4:7] - J2 10GE Base-CX4 Connector Board FPGA multi-gigabit transceiver Data Ports 4 through 7 are wired to a 10GE BaseCX4 connector J2 on the XM104. The four data port connections between the XM104 FMC HPC connector and the 10G Base-CX4 connector J2 are defined in Table 1-7.
Chapter 1: XM104 8. PCA9543 IIC Switch The board’s serial IIC bus is wired to an EEPROM and a two-channel NXP (formerly Philips Semiconductor) PCA9543 IIC bus switch on the XM104 (as shown in Figure 1-2, page 10). The IIC bus switch provides bidirectional bus isolation and isolates the fixed address Si570 and Si5368 devices from the main IIC bus of the board. The upstream side of the switch connects to the FMC HPC connector. Only one of the two downstream ports is utilized and it uses 3.3V signal levels.
Board Technical Description The two downstream IIC devices connected to the PCA9543 are at the following IIC addresses: • Si570 IIC address is at 0x5D • Si5368 IIC address is at 0x68 FMC XM104 Connectivity Card User Guide UG536 (v1.1) September 24, 2010 www.xilinx.
Chapter 1: XM104 9. Clocking Circuits Two programmable clock circuits are provided on the XM104: • Silicon Labs Si570 • Silicon Labs Si5368 A Silicon Labs Si570 serial IIC bus re-programmable clock source provides a low-jitter clock with a user-programmable output frequency from 10 to 810 MHz. The Si570 is located at IIC address 0x5D. The Si570 clock output (shown in Figure 1-2, page 10) is wired to a NB6L11 clock driver integrated circuit.
Board Technical Description Silicon Labs Si5368 A Silicon Labs Si5368 any-rate precision clock multiplier/jitter attenuator integrated circuit provides a wide range of clocking applications for the Xilinx board and XM104 combination. Table 1-13 shows the connections of the SI5368 differential clock outputs to the XM104 FMC HPC connector. Table 1-13 also shows connections of the clock outputs from the board to the inputs of the SI5368.
Chapter 1: XM104 Table 1-13: Si5368 Clock I/O Connections to FMC HPC Connector J1 (Cont’d) FMC Connector J1 Pin Signal Name I/O Standard Si5368 In/Out Si5368 G10 LA03_N LVCMOS_Vadj Output C3B G9 LA03_P LVCMOS_Vadj Output C2B H8 LA02_N LVCMOS_Vadj Output C1B H7 LA02_P LVCMOS_Vadj Input RESET_B Notes: 1. These signals are either inputs or outputs to the Si5368 depending upon the state of an internal Si5368 register.
