User guide

20 www.xilinx.com FMC XM104 Connectivity Card User Guide
UG536 (v1.1) September 24, 2010
Chapter 1: XM104
The Si5368 does not provide any clock outputs to the board without first going through
internal register initialization via the serial IIC bus interface from the bus master. Asserting
the reset input also requires re-initialization of the Si5368 registers to re-establish clock
outputs. The Si5368 is located at IIC address 0x68.
For additional application information on the Si5368 component see the manufacturer's
data sheet at www.silabs.com
.
G10 LA03_N LVCMOS_Vadj Output C3B
G9 LA03_P LVCMOS_Vadj Output C2B
H8 LA02_N LVCMOS_Vadj Output C1B
H7 LA02_P LVCMOS_Vadj Input RESET_B
Notes:
1. These signals are either inputs or outputs to the Si5368 depending upon the state of an internal Si5368 register.
Table 1-13: Si5368 Clock I/O Connections to FMC HPC Connector J1 (Cont’d)
FMC Connector J1
Pin
Signal Name I/O Standard Si5368 In/Out Si5368