- Silicon Laboratories, Inc. Clock User Manual

Si53xx-RM
44 Rev. 0.5
Table 9. Jitter Generation (Si5316, Si5324, Si5366, Si5368)
Parameter Symbol
Test Condition
1,2,3,4,5
Min Typ Max GR-253 Spec Unit
Measurement
Filter (MHz)
DSPLL
Bandwidth
2
Jitter Gen OC-192
J
GEN
0.02–80 120 Hz — 4.2 6.2 30 ps pp/0.3 UIpp ps
PP
—.27.42 N/A ps
rms
4–80 120 Hz — 3.7 6.4 10 ps pp/0.1 UIpp ps
PP
—.14.31 N/A ps
rms
0.05–80 120 Hz — 4.4 6.9 10 ps pp/0.1 UIpp ps
PP
— .26 .41 1.0 ps
rms
(0.01 UI
rms
ps
rms
Jitter Gen OC-48
J
GEN
0.012–20 120 Hz — 3.5 5.4 40.2 ps pp/
(0.1 UIpp)
ps
PP
—.27.41 4.02 ps
rms
(0.01 UI
rms
ps
rms
Notes:
1. Test condition: f
IN
= f
OUT
= 622.08 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time (20–80%), LVPECL
clock output.
2. BWSEL [1:0] loop bandwidth settings provided in Pin Descriptions.
3. 114.285 MHz 3rd OT crystal used as XA/XB input.
4. V
DD
= 2.5 V
5. T
A
= 85 °C
Table 10. Jitter Generation (Si5322, Si5325, Si5365, Si5367)
Parameter
Symbol
Test Condition
1,2
Min Typ Max Unit
Measurement
Filter (MHz)
DSPLL
Bandwidth
2
(kHz)
Jitter Gen OC-192 J
GEN
0.02–80 1096 — .49 — ps
rms
4–80 1096 — .23 — ps
rms
0.05–80 1096 — .47 — ps
rms
Jitter Gen OC-48 J
GEN
0.012–20 1096 — .48 — ps
rms
Notes:
1. Test condition: f
IN
= f
OUT
= 622.08 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time (20–80%), LVPECL
clock output.
2. BWSEL [1:0] loop bandwidth settings provided in Pin Descriptions.