Specifications

C8051F330/1
Rev. 1.1 149
16.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave pro-
cessors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first
sends an address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic
1; in
a data byte, the ninth bit is always set to logic
0.
Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is received, the
UART will generate an interrupt only if the ninth bit is logic
1 (RB80 = 1) signifying an address byte has been
received. In the UART interrupt handler, software will compare the received address with the slave's own assigned 8-
bit address. If the addresses match, the slave will clear its MCE0 bit to enable interrupts on the reception of the fol
-
lowing data byte(s). Slaves that weren't addressed leave their MCE0 bits set and do not generate interrupts on the
reception of the following data bytes, thereby ignoring the data. Once the entire message is received, the addressed
slave resets its MCE0 bit to ignore all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves,
thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master processor can be con
-
figured to receive all transmissions or a protocol can be implemented such that the master/slave role is temporarily
reversed to enable half-duplex transmission between the original master and slave(s).
Figure 16.6. UART Multi-Processor Mode Interconnect Diagram
Master
Device
Slave
Device
TXRX RX TX
Slave
Device
RX TX
Slave
Device
RX TX
V+