Specifications

C8051F330/1
164 Rev. 1.1
Figure 17.10. SPI0CKR: SPI0 Clock Rate Register
Bits 7-0: SCR7-SCR0: SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is configured for master
mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the
following equation, where SYSCLK is the system clock frequency and SPI0CKR is the 8-bit value
held in the SPI0CKR register.
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address: 0xA2
f
SCK
2000000
241+()×
--------------------------=
f
SCK
200kHz=
f
SCK
SYSCLK
2 SPI0CKR 1+()×
-------------------------------------------------=