Specifications

C8051F330/1
178 Rev. 1.1
18.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TH2 and TL2). Both 8-bit timers operate in auto-reload
mode as shown in
Figure 18.12. TMR2RLL holds the reload value for TL2; TMR2RLH holds the reload value for
TH2. The TR2 bit in TMR2CN handles the run control for TH2. TL2 is always running when configured for 8-bit
Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock source
divided by 8. The Timer
2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or the clock
defined by the Timer
2 External Clock Select bit (T2XCLK in TMR2CN), as follows:
The TF2H bit is set when TH2 overflows from 0xFF to 0x00; the TF2L bit is set when TL2 overflows from 0xFF to
0x00. When Timer
2 interrupts are enabled (IE.5), an interrupt is generated each time TH2 overflows. If Timer 2
interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is generated each time either TL2 or TH2 over
-
flows. When TF2LEN is enabled, software must check the TF2H and TF2L flags to determine the source of the
Timer
2 interrupt. The TF2H and TF2L interrupt flags are not cleared by hardware and must be manually cleared by
software
.
T2MH T2XCLK TH2 Clock Source T2ML T2XCLK TL2 Clock Source
0 0 SYSCLK / 12 0 0 SYSCLK / 12
0 1 External Clock / 8 0 1 External Clock / 8
1 X SYSCLK 1 X SYSCLK
Figure 18.12. Timer 2 8-Bit Mode Block Diagram
SYSCLK
TCLK
0
1
TR2
External Clock / 8
SYSCLK / 12
0
1
T2XCLK
1
0
TH2
TMR2RLH
Reload
Reload
TCLK
TL2
TMR2RLL
Interrupt
TMR2CN
T2SPLIT
TF2CEN
TF2LEN
TF2L
TF2H
T2XCLK
TR2
To ADC,
SMBus
To SMBus
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M