Specifications

C8051F330/1
Rev. 1.1 21
1.4. Programmable Digital I/O and Crossbar
C8051F330/1 devices include 17 I/O pins (two byte-wide Ports and one 1-bit-wide Port). The C8051F330/1 Ports
behave like typical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a dig
-
ital I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output. The
“weak pull-ups” that are fixed on typical 8051 devices may be globally disabled, providing power savings capabili
-
ties.
The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins (See Figure 1.7). On-chip
counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the controller can be con-
figured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows the user to select the
exact mix of general purpose Port I/O and digital resources needed for the particular application.
1.5. Serial Ports
The C8051F330/1 Family includes an SMBus/I
2
C interface, a full-duplex UART with enhanced baud rate configura-
tion, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive
use of the CIP-51's interrupts, thus requiring very little CPU intervention.
XBR0, XBR1,
PnSKIP Registers
Digital
Crossbar
Priority
Decoder
2
P0
I/O
Cells
P0.0
P0.7
8
PnMDOUT,
PnMDIN Registers
UART
(Internal Digital Signals)
Highest
Priority
Lowest
Priority
SYSCLK
2
SMBus
T0, T1
2
4
PCA
4
SPI
CP0
Outputs
2
P1
I/O
Cells
P1.0
P1.7
8
(Port Latches)
P0
(P0.0-P0.7)
(P1.0-P1.7)
8
8
P1
Figure 1.7. Digital Crossbar Diagram