Specifications

C8051F330/1
24 Rev. 1.1
1.8. Comparators
C8051F330/1 devices include an on-chip voltage comparator that is enabled/disabled and configured via user soft-
ware. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be
routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output. Comparator response time
is programmable, allowing the user to select between high-speed and low-power modes. Positive and negative hyster
-
esis are also configurable.
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may
be used as a “wake-up” source. Comparator0 may also be configured as a reset source.
Figure 1.10 shows the
Comparator0 block diagram.
Figure 1.10. Comparator0 Block Diagram
VDD
CPT0CN
Reset
Decision
Tree
+
-
Crossbar
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP0 +
P0.0
P0.2
P0.4
P0.6
CP0 -
P0.1
P0.3
P0.5
P0.7
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CPT0MX
CMX0N3
CMX0N2
CMX0N1
CMX0N0
CMX0P3
CMX0P2
CMX0P1
CMX0P0
CPT0MD
CP0RIE
CP0FIE
CP0MD1
CP0MD0
CP0
CP0A
P1.0
P1.2
P1.4
P1.6
P1.1
P1.3
P1.5
P1.7
CP0
Interrupt
0
1
0
1
CP0RIF
CP0FIF
0
1
CP0EN
0
1
EA