Specifications

C8051F330/1
8 Rev. 1.1
Figure 5.18. ADC Window Compare Example: Left-Justified Differential Data ...................49
Table 5.1. ADC0 Electrical Characteristics..........................................................................50
6. 10-BIT CURRENT MODE DAC (IDA0, C8051F330 ONLY)
Figure 6.1. IDA0 Functional Block Diagram ........................................................................51
Figure 6.2. IDA0 Data Word Mapping..................................................................................52
Figure 6.3. IDA0CN: IDA0 Control Register........................................................................53
Figure 6.4. IDA0H: IDA0 Data Word MSB Register ...........................................................53
Figure 6.5. IDA0L: IDA0 Data Word LSB Register.............................................................54
Table 6.1. IDAC Electrical Characteristics ..........................................................................55
7. VOLTAGE REFERENCE (C8051F330 ONLY)
Figure 7.1. Voltage Reference Functional Block Diagram....................................................57
Figure 7.2. REF0CN: Reference Control Register ................................................................58
Table 7.1. Voltage Reference Electrical Characteristics ......................................................58
8. COMPARATOR0
Figure 8.1. Comparator0 Functional Block Diagram ............................................................59
Figure 8.2. Comparator Hysteresis Plot.................................................................................60
Figure 8.3. CPT0CN: Comparator0 Control Register ...........................................................62
Figure 8.4. CPT0MX: Comparator0 MUX Selection Register..............................................63
Figure 8.5. CPT0MD: Comparator0 Mode Selection Register..............................................64
Table 8.1. Comparator Electrical Characteristics.................................................................65
9. CIP-51 MICROCONTROLLER
Figure 9.1. CIP-51 Block Diagram ........................................................................................67
Table 9.1. CIP-51 Instruction Set Summary.........................................................................69
Figure 9.2. Memory Map .......................................................................................................73
Table 9.2. Special Function Register (SFR) Memory Map..................................................75
Table 9.3. Special Function Registers ..................................................................................75
Figure 9.3. DPL: Data Pointer Low Byte ..............................................................................78
Figure 9.4. DPH: Data Pointer High Byte .............................................................................78
Figure 9.5. SP: Stack Pointer .................................................................................................79
Figure 9.6. PSW: Program Status Word ................................................................................79
Figure 9.7. ACC: Accumulator..............................................................................................80
Figure 9.8. B: B Register .......................................................................................................80
Table 9.4. Interrupt Summary...............................................................................................83
Figure 9.9. IE: Interrupt Enable .............................................................................................84
Figure 9.10. IP: Interrupt Priority ............................................................................................85
Figure 9.11. EIE1: Extended Interrupt Enable 1 .....................................................................86
Figure 9.12. EIP1: Extended Interrupt Priority 1.....................................................................87
Figure 9.13. IT01CF: INT0/INT1 Configuration Register ......................................................88
Figure 9.14. PCON: Power Control Register ..........................................................................90
10. RESET SOURCES
Figure 10.1. Reset Sources ......................................................................................................91
Figure 10.2. Power-On and VDD Monitor Reset Timing .......................................................92
Figure 10.3. VDM0CN: VDD Monitor Control ......................................................................93
Figure 10.4. RSTSRC: Reset Source Register.........................................................................95
Table 10.1. Reset Electrical Characteristics ...........................................................................96