Specifications

C8051F330/1
Rev. 1.1 9
11. FLASH MEMORY
Table 11.1. FLASH Electrical Characteristics .......................................................................98
Figure 11.1. FLASH Program Memory Map ........................................................................100
Figure 11.2. PSCTL: Program Store R/W Control................................................................100
Figure 11.3. FLKEY: FLASH Lock and Key Register .........................................................101
Figure 11.4. FLSCL: FLASH Scale Register ........................................................................101
12. EXTERNAL RAM
Figure 12.1. EMI0CN: External Memory Interface Control .................................................103
13. OSCILLATORS
Figure 13.1. Oscillator Diagram ............................................................................................105
Figure 13.2. OSCICL: Internal H-F Oscillator Calibration Register.....................................107
Figure 13.3. OSCICN: Internal H-F Oscillator Control Register ..........................................107
Figure 13.4. OSCLCN: Internal L-F Oscillator Control Register .........................................108
Figure 13.5. OSCXCN: External Oscillator Control Register...............................................110
Figure 13.6. CLKSEL: Clock Select Register .......................................................................112
Table 13.1. Internal Oscillator Electrical Characteristics.....................................................112
14. PORT INPUT/OUTPUT
Figure 14.1. Port I/O Functional Block Diagram ..................................................................113
Figure 14.2. Port I/O Cell Block Diagram.............................................................................114
Figure 14.3. Crossbar Priority Decoder with No Pins Skipped .............................................115
Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped ......................................116
Figure 14.5. XBR0: Port I/O Crossbar Register 0 .................................................................118
Figure 14.6. XBR1: Port I/O Crossbar Register 1 .................................................................119
Figure 14.7. P0: Port0 Register..............................................................................................121
Figure 14.8. P0MDIN: Port0 Input Mode Register ...............................................................121
Figure 14.9. P0MDOUT: Port0 Output Mode Register.........................................................122
Figure 14.10. P0SKIP: Port0 Skip Register...........................................................................122
Figure 14.11. P1: Port1 Register............................................................................................123
Figure 14.12. P1MDIN: Port1 Input Mode Register .............................................................123
Figure 14.13. P1MDOUT: Port1 Output Mode Register.......................................................124
Figure 14.14. P1SKIP: Port1 Skip Register...........................................................................124
Figure 14.15. P2: Port2 Register............................................................................................125
Figure 14.16. P2MDOUT: Port2 Output Mode Register.......................................................125
Table 14.1. Port I/O DC Electrical Characteristics ..............................................................126
15. SMBUS
Figure 15.1. SMBus Block Diagram .....................................................................................127
Figure 15.2. Typical SMBus Configuration ..........................................................................128
Figure 15.3. SMBus Transaction ...........................................................................................129
Table 15.1. SMBus Clock Source Selection.........................................................................132
Figure 15.4. Typical SMBus SCL Generation.......................................................................133
Table 15.2. Minimum SDA Setup and Hold Times .............................................................133
Figure 15.5. SMB0CF: SMBus Clock/Configuration Register .............................................134
Figure 15.6. SMB0CN: SMBus Control Register .................................................................136
Table 15.3. Sources for Hardware Changes to SMB0CN ....................................................137
Figure 15.7. SMB0DAT: SMBus Data Register ...................................................................138