Data Sheet

4.8.1 SPI Specification
Figure 4.1. SPI Interface Timing Parameters
Table 4.10. SPI Interface Timing Specifications
Symbol Description Min. Typ. Max. Unit
t
CLK
Clock period
19.23
1
ns
t
CLK_HI
Clock high 9 ns
t
CLK_LO
Clock low 9 ns
t
CS_DIS_MI
CS disable to MISO. VDD
IO
= 3.3V 8 ns
CS disable to MISO. VDD
IO
= 1.8V 10 ns
t
SU_CS
CS setup time 3 ns
t
SU_MO
MOSI setup time 3 ns
t
HD_MO
MOSI hold time 3 ns
t
CLKr_MI
, t
CLKf_MI
CLK to MISO out; VDD
IO
= 3.3V 10 ns
CLK to MISO out; VDD
IO
= 1.8V 21 ns
Note:
1. 19.23 ns = 1/52 MHz
2. MISO can optionally be latched either on rising edge or falling edge of CLK
3. All timing parameters valid for output load up to 2 mA
WFM200S Data Sheet
Electrical Specifications
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