Data Sheet

4.8.2 SDIO Specification
Figure 4.2. SDIO Interface Timing Parameters
Table 4.11. SDIO Interface Timing Specifications
Symbol Description Min Typ Max Unit Conditions
t
CLK_HS
Clock period in high speed
mode
19.23 ns CL ≤ 20pF
t
CLK_DS
Clock period in default speed
mode
38.46 ns CL ≤ 20pF
t
CLK_LO
Clock low time 9 ns CL≤ 20pF
t
CLK_HI
Clock high time 9 ns CL≤ 20pF
CMD, DAT0~3 Inputs (with reference to SDIO_CLK)
t
SU
Input Set time 3 ns CL≤ 20pF
t
HD
Input Hold time 3 ns CL≤ 20pF
CMD, DAT0~3 Outputs (with reference to SDIO_CLK)
t
ODLY_CLKr
,
t
ODLY_CLKf
Output delay time (relative to
rising and falling edge) for VDD
= 3.3V
11 ns VDD
IO
= 3.3V;
CL≤ 20pF
Output delay time (relative to
rising and falling edge) for VDD
= 1.8V
22 ns VDD
IO
= 1.8V;
CL≤ 20pF
t
OH
Output Hold time 3 ns CL≤ 20pF
1. Output data can be latched either on rising edge (HS mode) or falling edge (DS mode) of CLK
2. All timing parameters valid for output load of up to 2 mA
WFM200S Data Sheet
Electrical Specifications
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