Data Sheet

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Layout recommendations
silabs.com | Building a more connected world. Rev. 0.1 | 10
6 Layout recommendations
6.1 Generic RF Layout Considerations
For custom designs, use the same number of PCB layers as are present in the reference design whenever possible. Deviation from the
reference PCB layer count can cause different PCB parasitic capacitances, which can detune the matching network from its optimal form.
If a design with a different number of layers than the reference design is necessary, make sure that the distance between the top layer
and the first inner layer is similar to that found in the reference design, because this distance determines the parasitic capacitance value
to ground. Otherwise, detuning of the matching network is possible, and fine tuning of the component values may be required. The Silicon
Labs development kit uses a 1.6 mm thick FR4 PCB with the following board stack-up.
Figure 6.1 Reference design FR4 PCB stack-up
Use as much continuous and unified ground plane metallization as possible, especially on the top and bottom layers.
Use as many ground stitching vias, especially near the GND pins, as possible to minimize series parasitic inductance between the ground
pours of different layers and between the GND pins.
Use a series of GND stitching vias along the PCB edges and internal GND metal pouring edges. The maximum distance between the
vias should be less than lambda/10 of the 10th harmonic (the typical distance between vias on reference design is 1mm). This distance
is required to reduce the PCB radiation at higher harmonics caused by the fringing field of these edges.
For designs with more than two layers, it is recommended to put as many traces (even the digital traces) as possible in an inner layer
and ensure large, continuous GND pours on the top and bottom layers, while keeping the GND pour metallization unbroken beneath the
RF areas (between the antenna, matching network and the module). To benefit from parasitic decoupling capacitance, inner layer can be
used to route power supply with wide VBAT sub-plane and traces to increase parasitic capacitance with nearby ground layers.
Avoid using long and/or thin transmission lines to connect the RF related components. Otherwise, due to their distributed parasitic induct-
ance, some detuning effects can occur. Also shorten the interconnection lines as much as possible to reduce the parallel parasitic caps
to the ground. However, couplings between neighbor discretes may increase in this way.
Route traces (especially the supply and digital lines) on inner layers for boards with more than two layers.
To achieve good RF ground on the layout, it is recommended to add large, continuous GND metallization on the top layer in the area of
the RF section (at a minimum). Better performance may be obtained if this is applied to the entire PCB. To provide a good RF ground,
the RF voltage potentials should be equal along the entire GND area as this helps maintain good VBAT filtering. Any gap on each PCB
layer should ideally be filled with GND metal and the resulting sections on the top and bottom layers should be connected with as many
vias as possible. The reason for not using vias on the entire GND section is due to layout restrictions such as traces routed on other
layers or components on the bottom side.
Use tapered line between transmission lines with different width (i.e., different impedance) to reduce internal reflections.
Avoid using loops and long wires to obviate their resonances. They also work well as unwanted radiators, especially at the harmonics.
Avoid routing GPIO lines close or beneath the RF lines, antenna or crystal, or in parallel with a crystal signal. Use the lowest slew rate
possible on GPIO lines to decrease crosstalk to RF or crystal signals.
Use as many parallel grounding vias at the GND metal edges as possible, especially at the edge of the PCB and along the VBAT traces,
to reduce their harmonic radiation caused by the fringing field.
Place any high-frequency (MHz-ranged) crystal as close to the module as possible. External crystal load capacitors are not needed,
since there is an on-chip capacitance bank for this purpose. Thus, it is suggested that one select crystals with load capacitance require-
ments that can be supported by the module. This way, the crystal can be placed close to the chip pins and external capacitors are
not needed. Connect the crystal case to the ground using many vias to avoid radiation of the ungrounded parts. Do not leave any metal
unconnected and floating that may be an unwanted radiator. Avoid leading supply traces close or beneath the crystal or parallel with a
crystal signal or clock trace. If possible, use an isolating ground metal between the crystal and any nearby supply traces to avoid any
detuning effects on the crystal and to avoid the leakage of the crystal/clock signal and its harmonics to the supply lines. If possible, route
traces between crystal and module pins as differential signals to minimize area of trace loop.