Datasheet

SP001GBLRU800S02

240pin DDR2 800 Unbuffered DIMM

2 Rev 1.0 Aug 2007

1. Description

The SP

001GBLRU800S02 is a 128M x 8bits Double Data Rate SDRAM high-density for

DDR2-800. The SP001GBLRU800S02 consists of 8pcs CMOS 128Mx8 bits Double Data Rate

SDRAMs in 60 ball FBGA packages, and a 2048 bits serial EEPROM on a 240-pin printe

circuit board. The SP001GBLRU800S02 is a Dual In-Line Memory Module and is intended

for mounting into 240-pin edge connector sockets. Synchronous design allows precise

cycle control with the use of system clock. Data I/O transactions are possible on both

edges of DQS. Range of operation frequencies, programmable latencies allow the same

device to be useful for a variety of high bandwidth, high performance memory system

applications.

2. Features

․Fast data transfer rates: PC2-6400

․240-pin, unbuffered dual in-line memory module

․VDD = VDDQ = +1.8V, VDDSPD = +1.7V to +3.6V

․JEDEC standard 1.8V I/O (SSTL_18-compatible)

․Differential data strobe (DQS, DQS#) option

․Four-bit prefetch architecture

․DLL to align DQ and DQS transitions with CK

․Multiple internal device banks for concurrent operation

․Programmable CAS# latency (CL)

․Posted CAS# additive latency (AL)

․WRITE latency = READ latency - 1 tCK

․Programmable burst lengths: 4 or 8

․Adjustable data-output drive strength

․64ms, 8,192-cycle refresh

․On-die termination (ODT)

․60ball FBGA Leaded & Pb-Free (RoHS compliant) package