Datasheet

SP001GBLRU800S02
240pin DDR2 800 Unbuffered DIMM
6 Rev 1.0 Aug 2007
7. Command Truth Table
CKE
Command
Previous
Cycle
Current
Cycle
CS RAS CAS WE
BA0
,BA1
A10
A15-A11
,A9-A0
Note
(Extended) Mode Register Set
H H L L L L BA OP Code 1,2
Auto-Refresh
H H L L L H X X X 1
Self Refresh Entry
H L L L L H X X X 1
H X X X
Self Refresh Exit
L H
L H H H
X X X 1
Single Bank Precharge
H H L L H L BA L X 1,2
Precharge all Banks
H H L L H L X H X 1
Bank Activate
H H L L H H BA Row Address 1,2
Write
H H L H L L BA L Column Address 1,2,3
Write with Auto Precharge
H H L H L L BA H Column Address 1,2,3
Read
H H L H L H BA L Column Address 1,2,3
Read with Auto-Precharge
H H L H L H BA H Column Address 1,2,3
No Operation
H X L H H H X X X 1
Device Deselect
H X H X X X X X X 1
H X X X
Power Down Entry
H L
L H H H
X X X 1,4
H X X X
Power Down Exit
L H
L H H H
X X X 1,4
(H=Logic High Level, L=Logic Low Level, X=Don’t Care, OP Code=Operand Code)
NOTE ： 1. All DDR2 SDRAM commands are defined by states of /CS, /WE, /RAS, /CAS, and CKE at the rising edge of the clock.
2. Bank addresses (BA0, BA1) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode
Register.
3. Burst reads or writes at BL = 4 cannot be terminated. See sections “Reads interrupted by a Read” and “Writes interrupted
by a Write”.
4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the
refresh requirements.