User's Manual

SIM7600G User manual
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Figure 25: PCM_SYNC timing
Figure 26: EXT codec to MODULE timing
Figure 27: Module to EXT codec timing
Table 16: PCM timing parameters
Parameter
Description
Min.
Typ.
Max.
Unit
T(sync)
PCM_SYNC cycle time
–
125
–
μs
T(synch)
PCM_SYNC high level time
–
488
–
ns
T(syncl)
PCM_SYNC low level time
–
124.5
–
μs
T(clk)
PCM_CLK cycle time
–
488
–
ns
T(clkh)
PCM_CLK high level time
–
244
–
ns
T(clkl)
PCM_CLK low level time
–
244
–
ns
T(susync)
PCM_SYNC setup time high before falling edge of
PCM_CLK
–
244
–
ns
T(hsync)
PCM_SYNC hold time after falling edge of
PCM_CLK
–
244
–
ns
T(sudin)
PCM_IN setup time before falling edge of
PCM_CLK
60
–
–
ns
T(hdin)
PCM_IN hold time after falling edge of PCM_CLK
10
–
–
ns
T(pdout)
Delay from PCM_CLK rising to PCM_OUT valid
–
–
60
ns