Users Manual Part 1

SIM8260A_Hardware Design_V1.05
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
The 220nF AC capacitors should be placed near the PCIe_TX
Table 24: Definition of PCIe interface
Pin name
Pin
no.
Pin
characteristics
Functional
description
Comment
PCIe_REFCLK_P
B22
AIO
PCIe reference clock
plus
Required
85Ω differential
impedance
PCIe_REFCLK_M
A21
AIO
PCIe reference clock
minus
PCIe_TX0_M
B18
AO
PCIe transmit0 minus
PCIe_TX0_P
A17
AO
PCIe transmit0 plus
PCIe_TX1_M
B20
AO
PCIe transmit1 minus
PCIe_TX1_P
A19
AO
PCIe transmit1 plus
PCIe_RX0_M
A25
AI
PCIe receive0 minus
PCIe_RX0_P
B26
AI
PCIe receive0 plus
PCIe_RX1_M
A23
AI
PCIe receive1 minus
PCIe_RX1_P
B24
AI
PCIe receive1 plus
PCIe_CLKREQ
C21
DI
P3
PCIe clock request
PCIe_CLKREQ and
PCIe_WAKE need
pull up to VDD_EXT
externally,
Default as RC mode
PCIe_WAKE
C25
DI
P3
PCIe wake-up
PCIe_RST
C23
DO
P3
PCIe reset
PCIe interface layout guidelines:
 All other sensitive/high-speed signals must be far away PCIe signals.
 PCIe signals must be protected be far away noisy signals (clocks, SMPS).
 Each trace needs to be adjacent to a ground plane.

Require differential trace impedance is 85±10% Ω.
 The intra-lane length mismatch of the differential signal lanes is less than500um.
 Gap from other signals keeps 4xline width.
 Gap between Rx-to-Tx keeps 4xline width.
 Maximum PCB trace length cannot exceed 150mm outside of module, the shorter trace and better.
3.6.1 PCIe for W82
PCIe Gen3 lane0 can be connected to W82 as WLAN data interface, SIM8260As module serves as RC
and W82 module serves as EP. PCIe_CLKREQ and PCIe_WAKE already be pulled up to 1.8V in W82.
The details design please refer to the reference circuit document. The following figure is the PCIe