Hardware Design V1.00
Table Of Contents
- Version History
- 1. Introduction
- 2. SIM2000S Overview
- 3. Package Information
- 4. Application Interface
- 4.1. Power Supply
- 4.2. Power on/down Scenarios
- 4.3. Power Saving Mode
- 4.4. Serial Port and Debug Interface
- 4.5. RI behaviors
- 4.6. Audio Interfaces
- 4.7. RUIM Card Interface
- 4.8. PCM Interface
- 4.9. Keypad Interface
- 4.10. I2C Bus
- 4.11. General Purpose Input/Output (GPIO)
- 4.12. ADC
- 4.13. PWM
- 4.14. Network Status Indication
- 4.15. NETLIGHT Multiplexing Function
- 4.16. Operating Status Indication
- 4.17. Antenna Interface
- 5. PCB Layout
- 6. Electrical, Reliability and Radio Characteristics
- 7. Manufacturing
- 8. Appendix
Smart Machine Smart Decision
SIM2000S_Hardware_Design_V1.00 36 2014-02-27
Figure 30: EXT CODEC to MODULE timing
Figure 31: MODULE to EXT CODEC timing
Table 22: Timing parameters
Parameter Description Min Typ Max Unit
T(auxsync) PCMSYNC cycle time 125 s
T(auxsynch) PCMSYNC high time 62.4 62.5 s
T(auxsyncl) PCMSYNC low time 62.4 62.5 s
T(auxclk)* PCMCLK cycle time 7.8 s
T(auxclkh) PCMCLK high time 3.8 3.9 s
T(auxclkl) PCMCLK low time 3.8 3.9 s
T(suauxsync)
PCMSYNC setup time high before falling edge of
PCMCLK
1.95 s
T(hauxsync) PCMSYNC hold time after rising edge of PCMCLK 1.95 s
T(suauxdin) PCMDIN setup time before falling edge of PCMCLK 70 ns
T(hauxdin) PCMDIN hold time after falling edge of PCMCLK 20 ns
T(pauxdout) Delay from PCMCLK rising to PCMDOUT valid 50 ns
Note: T(auxclk) = 1/(128 KHz).