Service Manual

SRM9000 SERIES SERVICE MANUAL

• Modulation Balance adjustment

• Receiver front-end tuning

• Serial communications with alignment tool, microphone and control head

• Modem functionality for data modulation

• All signalling / CTCSS generation and decoding

• DSP Crystal Oscillator control

• Receiver muting control

• RSSI / AGC control

• AFC

• Tx / Rx switching and PTT control

• PLL lock detect

• Audio switching

• Power On/Off control

• Interface functionality with Option Boards and External Devices

• Battery voltage and Tx current monitor

3.4.2 DSP Clock Oscillator

The DSP is clocked by a 15.360MHz oscillator that consists of crystal X200 and an internal DSP oscillator.

Q200 forms a crystal switching circuit with C205 which, when activated by a command from the PLA, steers

the oscillator away from potential interfering frequencies.

3.4.3 PLA PWM

The PLA must supply several analogue signals to control radio tuning. It does this with several Pulse Width

Modulated (PWM) outputs.

The front-end tune signals (TUNE1-TUNE4) originate from the PLA in the form of PWM signals. The

values for these signals are stored in flash memory from radio alignment and selected depending on the

channel that the radio is currently tuned to. These signals are integrated by RC networks to provide the

analogue tuning voltages that are then applied to the tuning varicap diodes.

Other analogue PWM derived signals used are transmitter power (TX_PWR), receiver AGC voltage (AGC),

LED’s (RED/GREEN) and modulation balance (MOD_BAL).

Analogue inputs are monitored by four comparators comprising U301A-D and a ramp generator, the ramp

being derived from a PWM signal from the PLA.

Analogue voltages to be monitored such as PLL Loop Voltage (LOOP_VOLTS), key detect (KEY_DET),

battery voltage (BAT SENSE), transmitter current (TX_CURRENT), volume level (VOLUME) and external

sense (EXT_SENSE) are connected to the inverting inputs. The analogue voltages are compared with the

ramp voltage as they increase and the comparator switches at the point where the input voltage exceeds

the ramp. The PLA compares the time that this occurs with the PWM signal and converts it to a binary

value.

3.5 MEMORY

Memory consists of the internal DSP memory and an external 8MB non-volatile Flash Memory U202. When

power is off, all program SW and data are retained in Flash Memory. At power-on, a boot program

downloads the DSP and PLA SW from Flash Memory to their internal RAM’s for faster program execution

and access to data. PLA SW is loaded by the factory into the Flash Memory and can be updated via the