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Application Note

1 Overview

Vybrid controller solutions are built on the new

asymmetrical multiprocessing architecture using ARM

cores. The purpose of this application note is to provide an

overview of the power consumption Vybrid controller

solutions. The document is focused on normal run modes.

Several Vybrid use cases were defined and the power

consumptions measured using The Freescale Tower System

module (TWR-VF65GS10). To increase power efficiency,

several power supply options are presented, including ballast

transistor selection notes.

2 Vybrid controller solutions

overview

The Vybrid controller solutions are designed for rich

applications in real time. The primary features of the Vybrid

controller solutions include:

• Two ARM cores build on 40nm technology process

— Cortex-A5 core: 266, 400-500MHz – rich

applications; 8 stage pipeline; 1.57 DMIPS /

Document Number: AN4807

Rev. 0, 10/2013

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Vybrid controller solutions overview . . . . . . . . . . . . . 1

3. Power use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4. Working set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5. Vybrid power consumption . . . . . . . . . . . . . . . . . . . . . 5

6. Power consumption in selected use cases . . . . . . . . . . 6

7. Power consumption in special cases . . . . . . . . . . . . . . 7

8. Powering options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

9. Ballast transistor selection . . . . . . . . . . . . . . . . . . . . 17

10. Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

11. Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Vybrid Power Consumption and

Options

by Jiri Kotzian

Freescale Semiconductor, Inc.

Summary of content (20 pages)

PAGE 1
Freescale Semiconductor Application Note Document Number: AN4807 Rev. 0, 10/2013 Vybrid Power Consumption and Options by Jiri Kotzian Freescale Semiconductor, Inc. 1 Overview Vybrid controller solutions are built on the new asymmetrical multiprocessing architecture using ARM cores. The purpose of this application note is to provide an overview of the power consumption Vybrid controller solutions. The document is focused on normal run modes.
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Power use cases • MHz; ARM or Thumb mode (32- or 16 bit instructions) — Cortex-M4 core: 133-166MHz – Real time; 3 stage pipeline; 1.
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Working set Figure 1. Current measuring workstation The workstation is comprised of four precise multimeters, a power supply unit, a universal multimeter, and an oscilloscope. Current measurement units are synchronized using the external trigger input and the start button for measuring simultaneously. The oscilloscope is used to check the clock frequency using Vybrid clock-out pins.
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Working set Figure 2. The current measuring points on Vybrid tower module Vybrid Power Consumption and Options, Rev.
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Vybrid power consumption Measuring points are captured in the schematic in Table 2. The red circles mark the measuring points. Three measuring points used on-module jumper headers. The core current1 measuring point required a slight modification of the circuit. Additional jumper header was added on the module. Power rail I_3V3_MCU is used for the entire Vybrid SoC power supply, including the core.
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Power consumption in selected use cases Estimated currents: • For 25°C and 100% utilization it is up to 700mA. • For 85°C and 100% utilization it is up to 850mA. 6 Power consumption in selected use cases The following sections contain the results of measuring power supply currents in defined measuring points, in selected use cases. All data are measured in normal run mode at room temperature (22-25°C). 6.
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Power consumption in special cases Table 5. Linux results (continued) SDRAM (Vybrid) 1.5 119 173 External 3.3 33 100 Vybrid overall — — 496 Tower system overall 5V 760 3800 6.3 OOBE demo OOBE demo - Dual core on LINUX and MQX, QT, playing mp4 video in resolution 320x240 (TWR-LCD-RGB), MCC, WebGL, SDRAM / SRAM location. Table 6. OOBE results Nominal Power supply [V] Power Domain Power [mW] Current [mA] Core 1.2 289 355 SDRAM (Vybrid) 1.5 126 180 External 3.
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Power consumption in special cases 7.1 Consumption depending on Code placement Hello world application – print on serial channel. Table 8. Consumption depending on code placement Code placement Nominal Voltage [V] Current [mA] Power [mW] Note SRAM 1.2 148 182 SRAM current included SDRAM (DDR3) 1.5 + 3.3 184 + 106 = 290 227 +159 = 386 DDR3 memory consumption not included ~100mA / 1.5V QSPI 1.2 136 167 QSPI memory consumption not included ~50mA / 3.3V 7.
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Powering options 8 Powering options LDO or DC/DC converters can be used. The correct selection depends on the maximal current taken from a selected branch or rail. 8.1 Vybrid power rails Vybrid requires up to four different voltages; the first two are essential: • 3.3V for input/output pins and internal LDOs • 1.2V for core power supply and video ADC analog front end • 1.2V/1.5V for SDRAM interface (optional) • 5V for USB (optional) Two power rails must be supplied for normal run.
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Powering options Figure 3. Vybrid power supply block diagram 8.2 Power options The recommended circuit presented in Figure 3 (and used on the Vybrid tower module) is not very efficient. Particularly in the case of low power applications, better powering options can be defined. The powering options are presented in following paragraphs. Note that the efficiency of DC/DC converters (usually 90-95%) is not taken into account.
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Powering options • External DC/DC converter 8.3 External ballast transistor powered from VDD (default) The recommended circuit for general purpose application uses an external ballast transistor, which is powered from 3.3V to create a 1.2V power supply. This solution simple and suitable for a wide range of applications, but is very low-efficiency. Its simplicity is demonstrated in particular in the case that SDRAM memory is not used. The solution is also used on the Vybrid Freescale Tower module.
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Powering options The core power is: Total power on LDO with external ballast transistor is: The power efficiency in this case is: Such low power efficiency is due to the voltage drop on the transistor: as compared to 1.2V on the core. Moreover, the efficiency of the 3.3V DC/DC converter and 1.5V LDO are not included.
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Powering options Figure 5. External ballast transistor powered from VSDRAM The block scheme of power supply solution using external ballast transistor powered from VSDRAM on 1.5 voltage level is captured in Figure 5.
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Powering options Such power efficiency is due to the voltage drop on the transistor: as compared to 2.1V in the previous power option. Note than the efficiency of 3.3V DC/DC converter and of 1.5V DC/DC converter is not taken into account. This solution is suitable when: • applications with medium currents used; • SDRAM is used; • the thermal power loss on ballast transistor and the size of the transistor package is an issue. This solution is recommended especially for Linux applications. 8.
PAGE 15
Powering options %& ' !" #$ Figure 6. External DC/DC converter The block scheme of the power supply solution using external DC/DC converter power from 5V voltage level is captured in Figure 6. This solution is convenient for DDR3 usage.
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Powering options 5. Run the extensive part of the code, which requires more current. Low power stop mode sequence: 1. Stop extensive part of the code. 2. Switch to power from external ballast transistor using GPIO pin. a) Open right FET transistor to start feeding from external ballast transistor. b) Close left FET transistor to stop supplying from 1.2 DC/DC converter. c) Disable DC/DC. 3. LDO with external ballast transistor is used. 4. Jump in to low power stop mode. 5. Core is powered from internal LDO.
PAGE 17
Ballast transistor selection The complete Vybrid Reset/Boot sequence waveform is in Figure 7 and it is executed following steps: • Power On. • POR (400-500us) — Start—falling edge of RESET_B. — Wait for supply ramp 100us. — Internal LDOs (HPREG, LPREG) are enabled (1.2V ramp in the picture). — Wait for VREG to stabilize. — RESET sequence (fuse read, memory repair, etc.). — End—rising edge of RESET_B (trigger yellow triangle). • BootROM code (5-6ms) — Start. — Enable external Oscillator.
PAGE 18
Ballast transistor selection 9.1 Ballast transistor examples There exist many suitable transistors which can be used as the reference. Two examples were tested and measured. The first of them was on Semiconductor NJD2873T4 transistor, the default transistor on TWR-VF65GS10. The second transistor is much smaller. NXP PBSS4021NT is suitable for smaller currents and power dissipation.
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Conclusion Table 13. IC = 810mA (additional 2.2 load on 1.2V, external power supply) VC [V] 1.5 1.35 1.5 1.35 IB [mA] 6.5 >20/stopped 1.32 1.71 As demonstrated by measured data, it is possible to power the ballast transistor with a lower voltage than 3.3V to save the power and to increase power efficiency, if all requirements described above are fulfilled. 10 Conclusion This application note presents the Vybrid power consumption numbers and various powering options.
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