Datasheet

Vybrid Power Consumption and Options, Rev. 0
Freescale Semiconductor 17
Ballast transistor selection
The complete Vybrid Reset/Boot sequence waveform is in Figure 7 and it is executed following steps:
• Power On.
• POR (400-500us)
— Start—falling edge of RESET_B.
— Wait for supply ramp 100us.
— Internal LDOs (HPREG, LPREG) are enabled (1.2V ramp in the picture).
— Wait for VREG to stabilize.
— RESET sequence (fuse read, memory repair, etc.).
— End—rising edge of RESET_B (trigger yellow triangle).
• BootROM code (5-6ms)
—Start.
— Enable external Oscillator.
— Wait for external clock to stabilize (default 3ms in rev 1.1, can be set by fuses).
— Enable PLL, switch to PPL clock (edge on BTRL signal due to increase current demand).
— Image selection, image validation, etc.
— End.
• User code
If an additional DC/DC converter is used, no check of DC/DC converter voltage level is performed within
the Vybrid BootROM code. Ensure that the power supply voltage used for powering the external ballast
transistor is present and stable before the power supply is switched from low power LDO (LPREG) to
LDO with external ballast transistor (HPREG), which is 100us after the start of POR.
9 Ballast transistor selection
Selection of right ballast transistor sets several requirements captured in following points:
• Maximal current requirement: Despite the datasheet maximal values of the core current, the
maximal current strongly depends on the application and the environment temperature. From
700mA/25C to 850mA/85C. Select the transistor according to your application and the required
current.
• hFE /BCTRL requirement: BCTRL pin current must be less than 20mA. Required hFE can be
computed for maximal required current and maximal base current, which is 20mA. Minimal hFE
is 42.5, computed as 850mA / 20mA. Preferred hFE is 150 and more. Ensure that BCTRL voltage
is less than VDDREG – 0.5V due to limited output voltage swing of the BCTRL output circuit. For
example, if VDDREG = 3.0V, then BCTRL should not exceed 2.5V.
• Transistor total power dissipation requirement: Depends on maximal current and power supply
voltage level. If low current is used it is not necessary to use 15W DPAC package which is used on
the Vybrid Tower module. The transistor package size strongly depends on total power dissipation.
• Collector-Emitter saturation voltage requirement: Must be less than the difference between power
supply voltage and core voltage on maximal used current.
• Unity current gain Frequency requirement: More than 50MHz.