Datasheet

Vybrid Power Consumption and Options, Rev. 0

Freescale Semiconductor 5

Vybrid power consumption

Measuring points are captured in the schematic in Table 2. The red circles mark the measuring points.

Three measuring points used on-module jumper headers. The core current

measuring point required a

slight modification of the circuit. Additional jumper header was added on the module.

Power rail I_3V3_MCU is used for the entire Vybrid SoC power supply, including the core. To get current

for Vybrid input/output pins we need to subtract the core current using the following formula:



NOTE

The formula is used in measurements of current in selected use cases.

5 Vybrid power consumption

The current consumption strongly depends on the application, the run mode, and on the temperature. The

Vybrid SoC includes numerous gates. The application defines how many gates will be used during the run

of the application. The datasheet’s maximal current refers to the currents taken by component when all

gates are utilized. The real application does not use 100% of gates. As demonstrated by the real measured

currents, gate utilization is usually less than 50%, so current consumption is usually less than the half of

datasheet values.

5.1 Datasheet values

Datasheet values are presented in Table 2. See the latest revision of the Vybrid datasheet for the most

current values, available on freescale.com.

The parameters of silicon components depend on the temperature. In integrated circuits in particular, the

main dependencies are leakage currents. From an external point of view, the component current

consumption increases with the operating temperature.

1. Note that core current means the whole platform current which includes CA5, CM4, NIC, SRAM, etc.

Table 2. Vybrid current data from datasheet (rev. 4)

Vybrid Power Mode Functional Description Current (25°C)

RUN All functionality available 700mA

WAIT Core halted 600mA

LPRUN 24MHz operation. PLL bypassed 100mA

ULPRUN 32kHz or 128kHz operation, PLL off 50mA

STOP Lowest Power mode with all power retained, RAM retention 10mA

LPSTOP3 64kB SRAM retention, I/O states held, ADCs/DACs optionally power

gated. RTC functional, Wake-up on Interrupt.

100uA

LPSTOP2 16kB SRAM retention, I/O states held, ADCs/DACs optionally power

gated. RTC functional, Wake-up on Interrupt.

50uA

LPSTOP1 I/O states held, ADCs/DACs optionally power gated. RTC functional,

Wake-up on Interrupt.

25uA