Specifications

ManualsBrandsSimplicity ManualsLawn Mower7018H

TMS320LF/LC240x

DSP Controllers

Reference Guide

System and Peripherals

Literature Number: SPRU357

January 2000

Printed on Recycled Paper

Summary of content (477 pages)

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TMS320LF/LC240x DSP Controllers Reference Guide System and Peripherals Literature Number: SPRU357 January 2000 Printed on Recycled Paper
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
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Preface Read This First About This Manual This reference guide describes the architecture, system hardware, peripherals, and general operation of the TMS320x2407/x2406/x2404/x2402 digital signal processor (DSP) controllers. For a description of the CPU, assembly language instructions, and XDS510 emulator, refer to TMS320C24x DSP Controllers CPU and Instruction Set Reference Guide (SPRU160). This book should be used in conjunction with SPRU160.
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Notational Conventions an actual section name, enclosed in double quotes; the second parameter must be an address. - Square brackets [ ] identify an optional parameter. If you use an optional parameter, you specify the information within the brackets; you don’t enter the brackets themselves. Here’s an example of an instruction that has an optional parameter: LACC 16-bit constant [, shift] The LACC instruction has two parameters. The first parameter, 16-bit constant, is required.
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Information About Cautions and Warnings / Related Documentation From Texas Instruments Information About Cautions and Warnings This book may contain cautions. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment. Related Documentation From Texas Instruments The following books describe the ’C24x and related support tools.
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Related Documentation From Texas Instruments TMS320C1x/C2x/C2xx/C5x Assembly Language Tools User’s Guide (literature number SPRU018) describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the ’C1x, ’C2x, ’C2xx, and ’C5x generations of devices.
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Trademarks TMS320 DSP Designer’s Notebook: Volume 1 (literature number SPRT125) presents solutions to common design problems using ’C2x, ’C3x, ’C4x, ’C5x, and other TI DSPs. TMS320 Third-Party Support Reference Guide (literature number SPRU052) alphabetically lists over 100 third parties that provide various products that serve the family of TMS320 digital signal processors.
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Summarizes the TMS320 family of products. Introduces the TMS320x240x DSP controllers and lists their key features. 1.1 1.2 1.3 1.4 2 TMS320 Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320C240x Series of DSP Controllers . . . . . . . . . . . . . . . . . . .
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Contents 2.12 2.13 3 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 4.4 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Watchdog Suspend . . . . . . . . .
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Contents 6 Event Manager (EV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Describes the event manager (EV) module. Includes descriptions of the general-purpose timer, compare units, pulse-width modulation waveform circuits, capture units, and quadrature encoder pulse circuits. 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Event Manager (EV) Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents 6.10 7 7.3 7.4 7.5 7.6 7.7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 ADC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.1 Autoconversion Sequencer: Principle of Operation . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.2 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents 8.5 8.6 9 SCI Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.1 SCI Baud Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.1 SCI Communication Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.
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Contents 10 CAN Controller Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Describes the CAN controller module, interface signals, CAN peripheral registers, and mailbox RAM, layout, and operations. 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 Overview of the CAN Network . . . . . .
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Contents 11.3.1 WD Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.3.2 WD Reset Key Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.3.3 WD Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 12 ’240x–’240 Family Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents C TMS320F240x Boot ROM Loader: Protocols and Interfacing . . . . . . . . . . . . . . . . . . . . . . . . C.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.1.1 Boot-Load Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.2 Protocol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figures Figures 1–1 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 2–10 2–11 2–12 2–13 2–14 2–15 2–16 2–17 2–18 3–1 3–2 3–3 3–4 3–5 3–6 3–7 3–8 3–9 3–10 3–11 3–12 3–13 5–1 5–2 5–3 ’240x Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 ’240x Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 System Control and Status Register 1 (SCSR1) — Address 07018h . .
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Figures 5–4 5–5 5–6 5–7 5–8 5–9 5–10 6–1 6–2 6–3 6–4 6–5 6–6 6–7 6–8 6–9 6–10 6–11 6–12 6–13 6–14 6–15 6–16 6–17 6–18 6–19 6–20 6–21 6–22 6–23 6–24 6–25 6–26 6–27 6–28 6–29 6–30 6–31 6–32 6–33 xviii I/O Mux Control Register C (MCRC) — Address 7094h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Port A Data and Direction Control Register (PADATDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Port B Data and Direction Control Register (PBDATDIR) . . . . . . . . . . . . . . . . . .
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Figures 6–34 6–35 6–36 6–37 6–38 6–39 6–40 6–41 6–42 6–43 6–44 6–45 6–46 6–47 7–1 7–2 7–3 7–4 7–5 7–6 7–7 7–8 7–9 7–10 7–11 7–12 8–1 8–2 8–3 8–4 8–5 8–6 8–7 8–8 8–9 8–10 8–11 8–12 8–13 8–14 8–15 8–16 8–17 8–18 Quadrature Encoder Pulse (QEP) Circuit Block Diagram for EVB . . . . . . . . . . . . . . . . . . . 6-79 Quadrature Encoded Pulses and Decoded Timer Clock and Direction . . . . . . . . . . . . . . . 6-80 EVA Interrupt Flag Register A (EVAIFRA) — Address 742Fh . . . . . . . . . . . . . . . . . . . . .
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Figures 8–19 8–20 9–1 9–2 9–3 9–4 9–5 9–6 9–7 9–8 9–9 9–10 9–11 9–12 9–13 9–14 9–15 9–16 9–17 9–18 9–19 9–20 9–21 10–1 10–2 10–3 10–4 10–5 10–6 10–7 10–8 10–9 10–10 10–11 10–12 10–13 10–14 10–15 xx Transmit Data Buffer Register (SCITXBUF) — Address 7059h . . . . . . . . . . . . . . . . . . . . . 8-30 SCI Priority Control Register (SCIPRI) — Address 705Fh . . . . . . . . . . . . . . . . . . . . . . . . . 8-31 SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figures 10–16 10–17 10–18 10–19 10–20 10–21 10–22 10–23 11–1 11–2 11–3 11–4 13–1 13–2 13–3 13–4 13–5 13–6 13–7 13–8 13–9 B–1 C–1 C–2 C–3 C–4 C–5 C–6 Bit Configuration Register 1 (BCR1) — Address 7105h . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 CAN Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 Global Status Register (GSR) — Address 7107h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Tables Tables 1–1 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 3–1 3–2 3–3 4–1 5–1 5–2 5–3 5–4 5–5 5–6 5–7 5–8 5–9 5–10 6–1 6–2 6–3 6–4 6–5 6–6 6–7 6–8 6–9 xxii Hardware Features of ’240x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Description of Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 ’240x Interrupt Source Priority and Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Tables 6–10 6–11 6–12 6–13 6–14 6–15 6–16 6–17 6–18 7–1 7–2 7–3 7–4 7–5 7–6 7–7 7–8 8–1 8–2 8–3 8–4 8–5 9–1 9–2 9–3 10–1 10–2 10–3 10–4 10–5 11–1 11–2 11–3 13–1 13–2 13–3 13–4 13–5 13–6 13–7 13–8 13–9 13–10 13–11 Addresses of EVB Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 GP Timer Compare Output in Continuous Up-Counting Modes . . . . . . . . . . . . . . . . . . . . . 6-29 GP Timer Compare Output in Continuous Up-/Down-Counting Modes . .
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Tables A–1 B–1 B–2 C–1 xxiv Summary of Programmable Registers on the ’240x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Common Files For All Example Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Speeds at Which Baud Rate Locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Examples Examples 7–1 7–2 7–3 7–4 7–5 9–1 9–2 Conversion in Dual-Sequencer Mode Using SEQ1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Sequencer “Start/Stop” Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 MAX_CONV Register Bits Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 Calculating the Conversion Time for a Multiple Conversion Sequence With CPS = 0 and ACQ = 0: . . . .
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Chapter 1 Introduction The TMS320x240x series of devices are members of the TMS320 family of digital signal processors (DSPs) designed to meet a wide range of digital motor control (DMC) and other embedded control applications. This series is based on the ’C2xLP 16-bit, fixed-point, low-power DSP CPU, and is complemented with a wide range of on-chip peripherals and on-chip ROM or flash program memory, plus on-chip dual-access RAM (DARAM).
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TMS320 Family Overview 1.1 TMS320 Family Overview The TMS320 family consists of fixed-point, floating-point, multiprocessor digital signal processors (DSPs), and fixed-point DSP controllers. TMS320 DSPs have an architecture designed specifically for real-time signal processing. The ’240x series of DSP controllers combines this real-time processing capability with controller peripherals to create an ideal solution for control system applications.
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TMS320C240x Series of DSP Controllers 1.2 TMS320C240x Series of DSP Controllers Designers have recognized the opportunity to redesign existing digital motor control (DMC) systems to use advanced algorithms that yield better performance and reduce system component count.
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TMS320C240x Series of DSP Controllers of advanced control algorithms for techniques such as adaptive control, Kalman filtering, and state control. The ’240x DSP controllers offer reliability and programmability. Analog control systems, on the other hand, are hardwired solutions and can experience performance degradation due to aging, component tolerance, and drift.
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Peripheral Overview 1.3 Peripheral Overview The peripheral set for the ’240x devices includes: - Event Manager: Timers and PWM generators for digital motor control - CAN Interface: Controller Area Network (CAN) 2.
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’240x Highlights 1.4 ’240x Highlights - The ’2407 has an external memory interface and is intended primarily for emulation tools. - The ’2406 is similar to the ’240x but lacks external memory interface. - The ’2402 is a minimum-cost motor control device. The device configurations available and their features are shown in Table 1–1. Table 1–1.
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’240x Highlights Figure 1–1 provides a graphical overview of the devices. Figure 1–1.
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Chapter 2 System Configuration and Interrupts This chapter describes the system configuration registers and interrupts. It also explains how the peripheral interrupt expansion (PIE) is used to increase interrupt request capacity. Topic Page 2.1 Architecture Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Interrupt Priority and Vectors . . . .
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Architecture Summary 2.1 Architecture Summary The ’240x devices are implemented as ASIC customizable digital signal processors (cDSPs). The CPU, program ROM/FLASH is implemented as ASIC hard macros as shown in the shaded blocks in Figure 2–1. The CPU uses the LP256 hard macro which consists of the TMS320C2xx DSP CPU core, 544 x 16 words of dual-access RAM (DARAM), the analysis/JTAG logic, the internal memory interface, and the logic interface. The logic interface, however, is not used in the ’240x.
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Configuration Registers 2.2 Configuration Registers 2.2.1 System Control and Status Registers 1 and 2 (SCSR1, SCSR2) Figure 2–2.
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Configuration Registers Bits 11–9 PLL Clock prescale select. These bits select the PLL multiplication factor for the input clock. CLK PS2 CLK PS1 CLK PS0 System Clock Frequency 0 0 0 4 x Fin 0 0 1 2 x Fin 0 1 0 1.33 x Fin 0 1 1 1 x Fin 1 0 0 0.8 x Fin 1 0 1 0.66 x Fin 1 1 0 0.57 x Fin 1 1 0.5 x Fin 1 Note: Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 2-4 Fin is the input clock frequency. Reset OSC Fail.
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Configuration Registers Bit 1 Reserved Bit 0 ILLADR. Illegal Address detect bit If an illegal address has occurred this bit will be set. It is up to software to clear this bit following an illegal address detect. Note: An illegal address will cause an NMI. Figure 2–3.
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Configuration Registers Bit 3 Boot Enable This bit reflects the state of the BOOT_EN / XF pin at the time of reset. After reset and device has “Booted up”, this bit can be changed in software to re-enable Flash memory visibility, or return to active Boot ROM. Bit 2 0 Enable Boot ROM — Address space 0000 — 00FF is now occupied by the on-chip Boot ROM Block. Flash memory is totally disabled in this mode. Note: There is no on-chip boot ROM in ROM (i.e., “LC”240x) devices.
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Configuration Registers 2.2.2 Device Identification Number Register (DINR) Figure 2–4. Device Identification Number Register (DINR) — Address 701Ch 15 14 13 12 11 10 9 8 DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 R-x R-x R-x R-x R-x R-x R-x R-x 7 6 5 4 3 2 1 0 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 R-x R-x R-x R-x R-x R-x R-x R-x Note: R = Read access, -x = hardwired device-specific DIN value Bits 15–4 DIN15–DIN4.
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Interrupt Priority and Vectors 2.3 Interrupt Priority and Vectors A centralized interrupt expansion scheme is implemented in order to accommodate the large number of peripheral interrupts with the six maskable interrupts supported by the CPU. Table 2–2 provides the interrupt source priority and vectors for the ’240x devices. The details of the ’240x interrupt expansion scheme are explained in Chapter 2. Table 2–2.
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Interrupt Priority and Vectors Table 2–2.
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Interrupt Priority and Vectors Table 2–2.
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Interrupt Priority and Vectors Table 2–2.
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Peripheral Interrupt Expansion (PIE) 2.4 Peripheral Interrupt Expansion (PIE) The ’240x CPU supports one nonmaskable interrupt (NMI) and six maskable prioritized interrupt requests INT1–INT6 at the core level. The ’240x devices have many peripherals, and each peripheral is capable of generating one or more interrupts in response to many events at the peripheral level.
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Peripheral Interrupt Expansion (PIE) PIRQR1 PIRQR0 Figure 2–5.
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Peripheral Interrupt Expansion (PIE) 2.4.1 Interrupt Hierarchy The number of interrupt slots available is expanded by having two levels of hierarchy in the interrupt request system. Both the interrupt request/acknowledge hardware and the interrupt service routine software have two levels of hierarchy. 2.4.
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Peripheral Interrupt Expansion (PIE) 2.4.3 Interrupt Acknowledge The hierarchical interrupt expansion scheme requires one interrupt acknowledge signal for each peripheral interrupt request to the interrupt controller. When the CPU asserts its interrupt acknowledge, it simultaneously puts a value on the program address bus, which corresponds to the CPU interrupt being acknowledged.
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Interrupt Vectors 2.5 Interrupt Vectors When the CPU receives an interrupt request, it does not know which peripheral event caused the request. To enable the CPU to distinguish between all of these events, a unique peripheral interrupt vector is generated in response to an active peripheral interrupt request. This vector is loaded into the peripheral interrupt vector register (PIVR) in the PIE controller.
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Interrupt Vectors Figure 2–6.
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Interrupt Vectors 2.5.2 Software Hierarchy There are two levels of interrupt service routine hierarchy: the general interrupt service routine (GISR), and the specific interrupt service routine (SISR). There is one GISR for each maskable prioritized request (INT1–INT6) to the CPU which performs all necessary context saves before it fetches the peripheral interrupt vector from the PIVR. This vector is used to generate a branch to the SISR.
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Interrupt Operation Sequence 2.6 Interrupt Operation Sequence An interrupt generating event occurs in a peripheral. Refer to Figure 2–7 for ’240x interrupt response and flow in each module of the ’240x.The interrupt flag (IF) bit corresponding to that event is set in a register in the peripheral. If the corresponding interrupt enable (IE) bit is set, the peripheral generates an interrupt request to the PIE controller by asserting its PIRQ.
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Peripheral Flow Start Interrupt flag (IF) set in peripheral register (PR) Interrupt enable (IE) = 1 in PR? GISR Flow Peripheral CPU branches interrupt to occurs GISR Peripheral interrupt interrupt Peripheral occurs occurs User code saves context, reads PIVR for PIV value Interrupt generation awaits IE to be set or software clear of the IF bit set in peripheral register PIV = phantom vector? No Yes Interrupt service for phantom vector IE set by S/W No Yes PIE Flow CPU interrupt acknowledge cl
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Interrupt Latency 2.7 Interrupt Latency There are three components to interrupt latency: 1) Synchronization is the time it takes for the request generated in response to the occurrence of an interrupt generating event to be recognized by the PIE controller and converted into a request to the CPU. 2) Core Latency is the time it takes for the CPU to recognize the enabled interrupt request, clear it’s pipeline, and begin fetching the first instruction from the CPU’s interrupt vector table.
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Sample ISR Code 2.8 Sample ISR Code ; This sample ISR code illustrates how to branch to a SISR corresponding ; to a peripheral interrupt. No context save is done. ; Timer 1 period interrupt is assumed main code . B GISR2 ; This instruction resides at 0004h of PM . .
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CPU Interrupt Registers 2.9 CPU Interrupt Registers The CPU interrupt registers in the upper level of heirarchy include the following: - The interrupt flag register (IFR) - The interrupt mask register (IMR) 2.9.1 Interrupt Flag Register (IFR) The interrupt flag register (IFR), a 16-bit, memory-mapped register at address 0006h in data-memory space, is used to identify and clear pending interrupts. The IFR contains flag bits for all the maskable interrupts (INT1–INT6).
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CPU Interrupt Registers Figure 2–8. Interrupt Flag Register (IFR) — Address 0006h Note: 15–6 5 4 3 2 1 0 Reserved INT6 flag INT5 flag INT4 flag INT3 flag INT2 flag INT1 flag 0 RW1C-0 RW1C-0 RW1C-0 RW1C-0 RW1C-0 RW1C-0 0 = Always read as zeros, R = Read access, W1C = Write 1 to this bit to clear it, -0 = value after reset Bits 15–6 Reserved. These bits are always read as 0s. Bit 5 INT6. Interrupt 6 flag. This bit is the flag for interrupts connected to interrupt level INT6.
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CPU Interrupt Registers 2.9.2 Interrupt Mask Register (IMR) The IMR is a 16-bit, memory-mapped register located at address 0004h in data memory space. The IMR contains mask bits for all the maskable interrupt levels (INT1–INT6). Neither NMI nor RS is included in the IMR; thus, IMR has no effect on these interrupts. You can read the IMR to identify masked or unmasked interrupt levels, and you can write to the IMR to mask or unmask interrupt levels.
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CPU Interrupt Registers Bit 1 INT2. Interrupt 2 mask. This bit masks or unmasks interrupt level INT2. 0 1 Bit 0 INT1. Interrupt 1 mask. This bit masks or unmasks interrupt level INT1. 0 1 Note: 2-26 Level INT2 is masked. Level INT2 is unmasked. Level INT1 is masked. Level INT1 is unmasked. The IMR bits are not affected by a device reset.
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Peripheral Interrupt Registers 2.
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Peripheral Interrupt Registers 2.10.2 Peripheral Interrupt Request Registers (PIRQR0, 1, 2) The peripheral interrupt request registers (PIRQRx) enable: - The state of the peripheral interrupt requests to be read - A simulated assertion of a particular peripheral interrupt request PIRQR0 is shown in Figure 2–11, PIRQR1 is shown in Figure 2–12, and PIRQR2 is shown in Figure 2–13. Figure 2–11.Peripheral Interrupt Request Register 0 (PIRQR0) — Address 7010h 15 14 13 12 11 10 9 8 IRQ0.15 IRQ0.
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Peripheral Interrupt Registers Table 2–3. Peripheral Interrupt Request Descriptions (PIRQR0) (Continued) Bit position Interrupt Interrupt Description Interrupt Level IRQ 0.10 CMP2INT Compare 2 interrupt INT2 IRQ 0.11 CMP3INT Compare 3 interrupt INT2 IRQ 0.12 T1PINT Timer 1 period interrupt INT2 IRQ 0.13 T1CINT Timer 1 compare interrupt INT2 IRQ 0.14 T1UFINT Timer 1 underflow interrupt INT2 IRQ 0.15 T1OFINT Timer 1 overflow interrupt INT2 Figure 2–12.
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Peripheral Interrupt Registers Table 2–4. Peripheral Interrupt Request Descriptions (PIRQR1) Bit position Interrupt Interrupt Description Interrupt Level IRQ 1.0 T2PINT Timer 2 period interrupt INT3 IRQ 1.1 T2CINT Timer 2 compare interrupt INT3 IRQ 1.2 T2UFINT Timer 2 underflow interrupt INT3 IRQ 1.3 T2OFINT Timer 2 overflow interrupt INT3 IRQ 1.4 CAP1INT Capture 1 interrupt INT4 IRQ 1.5 CAP2INT Capture 2 interrupt INT4 IRQ 1.6 CAP3INT Capture 3 interrupt INT4 IRQ 1.
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Peripheral Interrupt Registers Table 2–5. Peripheral Interrupt Request Descriptions (PIRQR2) Bit position Interrupt Interrupt Description Interrupt Level IRQ 2.0 PDPINTB Power drive protection interrupt pin INT1 IRQ 2.1 CMP4INT Compare 4 interrupt INT2 IRQ 2.2 CMP5INT Compare 5 interrupt INT2 IRQ 2.3 CMP6INT Compare 6 interrupt INT2 IRQ 2.4 T3PINT Timer 3 period interrupt INT2 IRQ 2.5 T3CINT Timer 3 compare interrupt INT2 IRQ 2.
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Peripheral Interrupt Registers Bits 15–0 IACK0.15–IACK0.0. Peripheral interrupt acknowledge bits. Writing a 1 causes the corresponding peripheral interrupt acknowledge to be asserted, which clears the corresponding peripheral interrupt request. Note that asserting the interrupt acknowledge by writing to this register does not update the PIVR. Reading the register always returns zeros. Table 2–6.
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Peripheral Interrupt Registers Bit 15 Reserved. Reads return zero; writes have no effect. Bits 14–0 IACK1.14–IACK1.0. Bit behavior is the same as that of PIACKR0. Table 2–7. Peripheral Interrupt Acknowledge Descriptions (PIACKR1) Bit position Interrupt Interrupt Description Interrupt Level IAK 1.0 T2PINT Timer 2 period interrupt INT3 IAK 1.1 T2CINT Timer 2 compare interrupt INT3 IAK 1.2 T2UFINT Timer 2 underflow interrupt INT3 IAK 1.3 T2OFINT Timer 2 overflow interrupt INT3 IAK 1.
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Peripheral Interrupt Registers Table 2–8. Peripheral Interrupt Acknowledge Descriptions (PIACKR2) Bit position Interrupt Interrupt Description IAK 2.0 PDPINTB Power drive protection interrupt pin INT1 IAK 2.1 CMP4INT Compare 4 interrupt INT2 IAK 2.2 CMP5INT Compare 5 interrupt INT2 IAK 2.3 CMP6INT Compare 6 interrupt INT2 IAK 2.4 T3PINT Timer 3 period interrupt INT2 IAK 2.5 T3CINT Timer 3 compare interrupt INT2 IAK 2.6 T3UFINT Timer 3 underflow interrupt INT2 IAK 2.
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Reset Reset / Illegal Address Detect 2.11 Reset The ’240x devices have two sources of reset: - An external reset pin - A watchdog timer timeout The reset pin is an I/O pin. If there is an internal reset event (watchdog timer), the reset pin is put into output mode and driven low to indicate to external circuits that the ’240x device is resetting itself. The external reset pin and watchdog timer reset are ORed together to drive the reset input to the CPU. 2.
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External Interrupt Control Registers 2.13 External Interrupt Control Registers The two external interrupt control registers that control and monitor XINT1 and XINT2 pin activities are XINT1CR and XINT2CR. 2.13.1 External Interrupt 1 Control Register (XINT1CR) Figure 2–17.
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External Interrupt Control Registers 2.13.2 External Interrupt 2 Control Register (XINT2CR) Figure 2–18.
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Chapter 3 Memory This chapter describes the RAM, ROM, and Flash availability on the ’240x. In addition to dual-access RAM (DARAM – B0, B1, B2), which is part of the CPU core, the ’240x devices include flash EPROM or ROM for additional onchip program memory. Devices with the “LF” prefix are flash devices and devices with the “LC” prefix are ROM devices.
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Factory Factory Masked Masked On-Chip On-Chip ROM ROM / Flash 3.1 Factory Masked On-Chip ROM The on-chip ROM in ROM devices is mapped in program memory space. This ROM is always enabled since these devices lack an external memory interface. This ROM is programmed with customer-specific code. 3.2 Flash The on-chip flash in flash devices is mapped in program memory space. This flash memory is always enabled in devices that lack an external memory interface.
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Overview of Memory and I/O Spaces 3.3 Overview of Memory and I/O Spaces The ’240x design is based on an enhanced Harvard architecture. These devices have multiple memory spaces accessible on three parallel buses: a program address bus (PAB), a data-read address bus (DRAB), and a data-write address bus (DWAB). Each of the three buses access different memory spaces for different phases of the device’s operation.
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Overview of Memory and I/O Spaces Figure 3–1.
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Overview of Memory and I/O Spaces Figure 3–2.
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Overview of Memory and I/O Spaces Figure 3–3.
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Overview of Memory and I/O Spaces Figure 3–4.
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Overview of Memory and I/O Spaces Figure 3–5.
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Overview of Memory and I/O Spaces Figure 3–6.
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Program Memory 3.4 Program Memory In addition to storing the user code, the program memory also stores immediate operands and table information. A maximum of 64K 16-bit words can be addressed in the program memory for ’240x. This number includes on-chip DARAM and flash EEPROM/ROM. Whenever an off-chip memory location needs to be accessed, the appropriate control signals for external access (PS, DS, STRB, etc.) are automatically generated. Figure 3–7 shows the ’LF2407 program memory map. Figure 3–7.
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Program Memory - MP/MC pin. The level on the MP/MC pin determines whether program instructions are read from on-chip flash/ROM or external memory: J MP/MC = 0. The device is configured in microcontroller mode. The onchip ROM/flash EEPROM is accessible. The device fetches the reset vector from on-chip memory. Accesses to program memory addresses 0000h–7FFFh will be made to on-chip memory in the case of ’2407. J MP/MC = 1. The device is configured in microprocessor mode.
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Data Memory 3.5 Data Memory Data memory space addresses up to 64K of 16-bit words. 32K words are internal memory (0000h to 7FFFh). Internal data memory includes memorymapped registers, DARAM, and peripheral memory-mapped registers. The remaining 32K words of memory (8000h to FFFFh) form part of the external data memory. Note that addresses 8000h–FFFFh are not accessible in ’2406, ’2404, and ’2402. Figure 3–8 shows the data memory map for the ’2407.
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Data Memory Figure 3–8.
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Data Memory Figure 3–9. Data Memory Pages DP Value Data Memory Offset 0000 0000 0 . . . 0000 0000 0 0000 0000 1 . . . 0000 0000 1 0000 0001 0 . . . 0000 0001 0 000 0000 . . . 111 1111 000 0000 . . . 111 1111 000 .0000 . . 111 1111 Page 1: 0080h–00FFh . . . . . . . . . . . . . . . . . . 1111 1111 1 . . . 1111 1111 1 000 0000 . . . 111 1111 Page 0: 0000h–007Fh Page 2: 0100h–017Fh .
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Data Memory - The scratch-pad RAM block (B2) includes 32 words of DARAM that pro- vide for variable storage without fragmenting the larger RAM blocks, whether internal or external. This RAM block supports dual-access operations and can be addressed via any data-memory addressing mode. Table 3–1 shows the address map of data page 0. Table 3–1.
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I/O Space 3.6 I/O Space The I/O-space memory addresses up to 64K 16-bit words. Figure 3–10 shows the I/O space address map for the ’240x. Figure 3–10. I/O Space Address Map for ’240x 0000h External FEFF FF00 ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ Reserved/Illegal FF0E FF0F FF10 Flash control mode register† Reserved FFFE FFFF Wait-state generator control register‡ † Available only on Flash devices. ‡ Available only on devices with external memory interface.
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XMIF Qualifier Signal Description 3.7 XMIF Qualifier Signal Description The ’240x can address the following memory sizes in each of the external memory spaces: Ext. Memory Space Size (in words) Qualifier signal (strobe) Program space 64K PS Data space 64K DS I/O space 64K IS The signals that define the XMIF are given in Table 3–2. Table 3–2. XMIF Signal Descriptions Signal/s name Signal description A(0:15) External 16-bit unidirectional address bus.
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XMIF Qualifier Signal Description Figure 3–11.
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XMIF Qualifier Signal Description Figure 3–12.
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Program Program and and Data Data Spaces Spaces / I/O Space 3.8 Program and Data Spaces PS and STRB are inactive (high) for accesses to on-chip program memory and data memory. The external data and address busses are active only when accesses are made to external memory locations, except when in bus visibility (BVIS) mode (see section 3.10, Wait-State Generation). Two cycles are required on all external writes, including a half-cycle before WE goes low and a half-cycle after WE goes high.
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Wait-State Generation 3.10 Wait-State Generation Wait states are necessary when you want to interface the ’240x with slower external logic and memory. By adding wait states, you lengthen the time the CPU waits for external memory or an external I/O port to respond when the CPU reads from or writes to that memory or port. Specifically, the CPU waits one extra cycle (one CLKOUT cycle) for every wait state. The wait states operate on CLKOUT cycle boundaries.
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Wait-State Generation Figure 3–13. ’240x Wait-State Generator Control Register (WSGR) — I/O-Space Address FFFFh (’240x) Note: 15–11 10–9 8–6 5–3 2–0 Reserved BVIS ISWS DSWS PSWS 0 W-11 W-111 W-111 W-111 0 = Always read as zeros: W = Write access: -n = value after reset Bits 15–11 Reserved. Bits 15–11 are reserved and always read as 0s. Bits 10–9 Bus visibility modes. Bits 10–9 allow selection of various bus visibility modes while running from internal program and/or data memory.
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Wait-State Generation Table 3–3.
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Chapter 4 Clocks The ’240x devices use the phase-locked loop (PLL) circuit embedded in the ’240x CPU core to synthesize the on-chip clocks from a lower frequency external clock. There is no means of bypassing the PLL. Topic Page 4.1 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3 Watchdog Timer Clock . . . .
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Pins Pins / Phase-Locked Loop / Watchdog Timer Clock 4.1 Pins There are three device pins associated with clocks: - XTAL1/CLKIN – This is the clock input from the external crystal to the on- chip oscillator. If an external oscillator is used, its output must be connected to this pin. - XTAL2 – This is the clock output from the on-chip oscillator to drive the ex- ternal crystal. - CLKOUT/IOPE0 – This is the clock output pin. It is multiplexed with GPIO pin IOPE0.
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Low-Power Modes 4.3.1 Watchdog Suspend WDCLK is stopped when the CPU’s suspend signal goes active. This is achieved by stopping the clock input to the clock divider which generates WDCLK from CLKIN. 4.4 Low-Power Modes The ’240x has an IDLE instruction. When executed, the IDLE instruction stops the clocks to all circuits in the CPU; however, the clock output from the CPU continues to run. With this instruction, the CPU clocks can be shut down to save power.
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Low-Power Modes Table 4–1.
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Low-Power Modes 4.4.2.4 Peripheral interrupts All peripheral interrupts, if enabled locally and globally, can cause the device to exit IDLE1 mode. INTM must be enabled for LPM operation. If the IMR bits are not enabled, the device “wakes up” from LPM mode and executes the next instruction. Since no ISRs are executed, the peripheral flags must be cleared. For example, when XINT1 is used to “wake up” the device from LPM0, two things can happen based on how the XINT1 interrupt is configured.
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Chapter 5 Digital Input/Output (I/O) The digital I/O ports module provides a flexible method for controlling both dedicated I/O and shared pin functions. All I/O and shared pin functions are controlled using nine 16-bit registers. These registers are divided into two types: - I/O MUX Control registers (MCRx) – Used to control the multiplexor selec- tion that chooses between the primary function of a pin or the generalpurpose I/O function.
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Digital I/O Ports Register Implementation on ’240x Devices 5.1 Digital I/O Ports Register Implementation on ’240x Devices Table 5–1 lists the registers available to the digital I/O module as implemented on the ’240x devices. These registers are memory-mapped to data space from 7090h through 709Fh. All reserved registers and bits are unimplemented: reads return zero and writes have no effect.
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Digital I/O Ports Register Implementation on ’240x Devices Table 5–1.
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Differences in GPIO Implementation in ’240x 5.2 Differences in GPIO Implementation in ’240x There are several differences in the GPIO implementation in ’240x when compared with ’241/’242/’243. When the bit value in an MCRx register (OCRx register in ’24x) is 1, the primary function is always chosen. By the same token, when the bit value is 0, the GPIO function is always chosen. There are no exceptions, as in the case of ’24x, where XF, BIO, and CLKOUT pins have a different configuration.
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I/O MUX Control Registers 5.3 I/O MUX Control Registers There are three I/O mux control registers: I/O mux control register A (MCRA), I/O mux control register B (MCRB), and I/O mux control register C (MCRC). I/O Mux Control Register A 5.3.1 Figure 5–2. I/O Mux Control Register A (MCRA) — Address 7090h 15 14 13 12 11 10 9 8 MCRA.15 MCRA.14 MCRA.13 MCRA.12 MCRA.11 MCRA.10 MCRA.9 MCRA.8 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 7 6 5 4 3 2 1 0 MCRA.7 MCRA.6 MCRA.5 MCRA.
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I/O MUX Control Registers Table 5–2. I/O Mux Control Register A (MCRA) Configuration Pin Function Selected Note: 5.3.2 Bit # Name.bit # (MCA.n = 1) (Primary) (MCA.n = 0) (Secondary) 0 MCRA.0 SCITXD IOPA0 1 MCRA.1 SCIRXD IOPA1 2 MCRA.2 XINT1 IOPA2 3 MCRA.3 CAP1/QEP1 IOPA3 4 MCRA.4 CAP2/QEP2 IOPA4 5 MCRA.5 CAP3 IOPA5 6 MCRA.6 CMP1 IOPA6 7 MCRA.7 CMP2 IOPA7 8 MCRA.8 CMP3 IOPB0 9 MCRA.9 CMP4 IOPB1 10 MCRA.10 CMP5 IOPB2 11 MCRA.11 CMP6 IOPB3 12 MCRA.
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I/O MUX Control Registers Table 5–3. I/O Mux Control Register B (MCRB) Pin Function Selected Notes: Bit # Name.bit # (MCB.n = 1) (Primary) (MCB.n = 0) (Secondary) 0 MCRB.0 W/R IOPC0 1 MCRB.1 BIO IOPC1 2 MCRB.2 SPISIMO IOPC2 3 MCRB.3 SPISOMI IOPC3 4 MCRB.4 SPICLK IOPC4 5 MCRB.5 SPISTE IOPC5 6 MCRB.6 CANTX IOPC6 7 MCRB.7 CANRX IOPC7 8 MCRB.8 XINT2/ADCSOC IOPD0 9 MCRB.9 EMU0 Reserved 10 MCRB.10 EMU1 Reserved 11 MCRB.11 TCK Reserved 12 MCRB.
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I/O MUX Control Registers 5.3.3 I/O Mux Output Control Register C Figure 5–4. I/O Mux Control Register C (MCRC) — Address 7094h 15 14 13 12 11 10 9 8 Reserved Reserved MCRC.13 MCRC.12 MCRC.11 MCRC.10 MCRC.9 MCRC.8 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 7 6 5 4 3 2 1 0 MCRC.7 MCRC.6 MCRC.5 MCRC.4 MCRC.3 MCRC.2 MCRC.1 MCRC.0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-1 Note: R = Read access, W = Write access, -0 = value after reset Table 5–4.
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Data and Direction Control Registers 5.4 Data and Direction Control Registers There are six data and direction control registers. Refer to Table 5–1, ’240x Digital I/O Port Control Registers Implementation, on page 5-3 for the address locations of each register. Figure 5–5.
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Data and Direction Control Registers Table 5–5. PADATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O; i.e., Secondary Function) I/O Port Data Bit Pin Name IOPA0 SCITXD/IOPA0 IOPA1 SCIRXD/IOPA1 IOPA2 XINT1/IOPA2† IOPA3 CAP1/QEP1/IOPA3 IOPA4 CAP2/QEP2/IOPA4 IOPA5 CAP3/IOPA5 IOPA6 CMP1/IOPA6 IOPA7 CMP2/IOPA7 † There is no IOPA2 pin in ’2402 devices.
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Data and Direction Control Registers Figure 5–6. Port B Data and Direction Control Register (PBDATDIR) 15 14 13 12 11 10 9 8 B7DIR B6DIR B5DIR B4DIR B3DIR B2DIR B1DIR B0DIR RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 7 6 5 4 3 2 1 0 IOPB7 IOPB6 IOPB5 IOPB4 IOPB3 IOPB2 IOPB1 IOPB0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 Note: R = Read access, W = Write access, -0 = value after reset Bits 15–8 Bits 7–0 BnDIR 0 Configure corresponding pin as an input.
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Data and Direction Control Registers Figure 5–7. Port C Data and Direction Control Register (PCDATDIR) 15 14 13 12 11 10 9 8 C7DIR C6DIR C5DIR C4DIR C3DIR C2DIR C1DIR C0DIR RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 7 6 5 4 3 2 1 0 IOPC7 IOPC6 IOPC5 IOPC4 IOPC3 IOPC2 IOPC1 IOPC0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 Note: R = Read access, W = Write access, -0 = value after reset Bits 15–8 Bits 7–0 CnDIR 0 Configure corresponding pin as an input.
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Data and Direction Control Registers Figure 5–8. Port D Data and Direction Control Register (PDDATDIR) 15–9 8 Reserved D0DIR RW-0 7–1 0 Reserved IOPD0 RW-0 Note: R = Read access, W = Write access, -0 = value after reset Bits 15–9 Reserved Bit 8 D0DIR 0 Configure corresponding pin as an input. 1 Configure corresponding pin as an output. Bits 7–1 Reserved Bit 0 IOPD0 If D0DIR = 0, then: 0 Corresponding I/O pin is read as a low. 1 Corresponding I/O pin is read as a high.
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Data and Direction Control Registers Figure 5–9. Port E Data and Direction Control Register (PEDATDIR) 15 14 13 12 11 10 9 8 E7DIR E6DIR E5DIR E4DIR E3DIR E2DIR E1DIR E0DIR RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 7 6 5 4 3 2 1 0 IOPE7 IOPE6 IOPE5 IOPE4 IOPE3 IOPE2 IOPE1 IOPE0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 Note: R = Read access, W = Write access, -0 = value after reset Bits 15–8 Bits 7–0 EnDIR 0 Configure corresponding pin as an input.
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Data and Direction Control Registers Figure 5–10. Port F Data and Direction Control Register (PFDATDIR) 15 14 13 12 11 10 9 8 Reserved F6DIR F5DIR F4DIR F3DIR F2DIR F1DIR F0DIR RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 7 6 5 4 3 2 1 0 Reserved IOPF6 IOPF5 IOPF4 IOPF3 IOPF2 IOPF1 IOPF0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 Note: R = Read access, W = Write access, -0 = value after reset Bit 15 Reserved Bits 14–8 FnDIR 0 Configure corresponding pin as an input.
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Chapter 6 Event Manager (EV) This chapter describes the ’240x Event Manager (EV) module. Most of the EV pins are shared with general-purpose digital I/O signals. This pin sharing and how it is controlled is described in Chapter 5, Digital Input/Output (I/O). The EV module provides a broad range of functions and features that are particularly useful in motion control and motor control applications.
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Event Manager (EV) Functional Blocks 6.1 Event Manager (EV) Functional Blocks All devices of the ’240x family, with the exception of the ’2402, have two event managers, EVA and EVB. These two event managers are exactly identical to each other in terms of functionality and register mapping/bit definition. For the sake of brevity, only the functionality of EVA is explained. Minor differences (such as naming conventions and register addresses) are highlighted as appropriate.
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Event Manager (EV) Functional Blocks Figure 6–1.
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Event Manager (EV) Functional Blocks Figure 6–2.
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Event Manager (EV) Functional Blocks 6.1.1 Differences Between ’C240 EV and ’240x EV - The single-up count and single-up/down count modes have been re- moved from the remaining GP timers. Software change: The four timer modes are now decoded with TMODE1–0. This decoding is different from the ’C240 EV. TMODE2 is now a reserved bit. - There is no 32-bit timer mode.
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Event Manager (EV) Functional Blocks - Software writing a 1 to the interrupt flag, which has been identified by the interrupt vector ID, is required to clear the flag. Reading the interrupt vector ID no longer automatically clears the associated flag. - PDPINTA/B is now enabled following reset. - Only one write is required to initialize COMCONA/B, not two as on the ’C240. 6.1.
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Event Manager (EV) Functional Blocks Table 6–1.
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Event Manager (EV) Functional Blocks Table 6–2. Event Manager B Pins 6.1.
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Event Manager (EV) Functional Blocks 6.1.4 EV Registers The Event Manager registers occupy two 64-word (16-bit) frames of address space. The Event Manager module decodes the lower 6-bits of the address; while the upper 10 bits of the address are decoded by the peripheral address decode logic, which provides a module select to the Event Manager when the peripheral address bus carries an address within the range designated for the EV on that device.
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Event Manager (EV) Functional Blocks - CPU response. On receipt of INT1, 2, 3, or 4 interrupt request, the respec- tive bit in the CPU interrupt flag register (IFR) will be set. If the corresponding interrupt mask register (IMR) bit is set and INTM bit is cleared, then the CPU recognizes the interrupt and issues an acknowledgement to the PIE. Following this, the CPU finishes executing the current instruction and branches to the interrupt vector corresponding to INT1, 2, 3, or 4.
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Event Manager (EV) Register Addresses 6.2 Event Manager (EV) Register Addresses Table 6–3 through Table 6–10 display the addresses of the Event Manager registers. Table 6–3.
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Event Manager (EV) Register Addresses Table 6–6. Addresses of EVB Compare Control Registers Address Register Name 7511h COMCONB Compare control register 7513h ACTRB Compare action control register 7515h DBTCONB Dead-band timer control register 7517h CMPR4 Compare register 4 7518h CMPR5 Compare register 5 7519h CMPR6 Compare register 6 Table 6–7.
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Event Manager (EV) Register Addresses Table 6–9. Addresses of EVA Interrupt Registers Address Register Name 742Ch EVAIMRA Interrupt mask register A 742Dh EVAIMRB Interrupt mask register B 742Eh EVAIMRC Interrupt mask register C 742Fh EVAIFRA Interrupt flag register A 7430h EVAIFRB Interrupt flag register B 7431h EVAIFRC Interrupt flag register C Table 6–10.
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General-Purpose (GP) Timers 6.3 General-Purpose (GP) Timers There are two general-purpose (GP) timers in each module.
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General-Purpose (GP) Timers Figure 6–3.
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General-Purpose (GP) Timers - Direction input, TDIRA/B, for use by the GP timers in directional up-/down- counting mode. - Reset signal, RESET. When a timer is used with the QEP circuit, the QEP circuit generates both the timer’s clock and the counting direction.
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General-Purpose (GP) Timers GP Timer Compare Registers The compare register associated with a GP timer stores the value to be constantly compared with the counter of the GP timer. When a match happens, the following events occur: - A transition occurs on the associated compare output according to the bit pattern in GPTCONA/B. - The corresponding interrupt flag is set. - A peripheral interrupt request is generated if the interrupt is unmasked.
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General-Purpose (GP) Timers a period in order to change the timer period and the width of the PWM pulse for the period that follows. On-the-fly change of the timer period value, in the case of PWM generation, means on-the-fly change of PWM carrier frequency. Caution : The period register of a GP timer should be initialized before its counter is initialized to a non-zero value. Otherwise, the value of the period register will remain unchanged until the next underflow.
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General-Purpose (GP) Timers GP timer 4 (EVB) can be used with the QEP circuits, in directional up-/downcounting mode. In this case, the QEP circuits provide both the clock and direction inputs to the timer. A wide range of prescale factors are provided for the clock input to each GP timer. QEP-Based Clock Input The quadrature encoder pulse (QEP) circuit, when selected, can generate the input clock and counting direction for GP timer 2/4 in the directional up-/downcounting mode.
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General-Purpose (GP) Timers This allows the desired synchronization between GP timer events. Since each GP timer starts the counting operation from its current value in the counter register, one GP timer can be programmed to start with a known delay after the other GP timer. Starting the A/D Converter with a Timer Event The bits in GPTCONA/B can specify that an ADC start signal be generated on a GP timer event such as underflow, compare match, or period match.
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General-Purpose (GP) Timers a period event happens when the value of the timer counter is the same as that of the period register. The overflow, underflow, and period interrupt flags of the timer are set one clock cycle after the occurrence of each individual event. Note that the definition of overflow and underflow is different from their conventional definitions. 6.3.
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General-Purpose (GP) Timers One clock cycle after the GP timer becomes 0, the underflow interrupt flag of the timer is set. A peripheral interrupt request is generated by the flag if it is unmasked. An ADC start is sent to the ADC module at the same time if the underflow interrupt flag of this timer has been selected by appropriate bits in GPTCONA/B to start ADC. The overflow interrupt flag is set one clock cycle after the value in TxCNT matches FFFFh.
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General-Purpose (GP) Timers Figure 6–4. GP Timer Continuous Up-Counting Mode (TxPR = 3 or 2) TxPR=4–1=3 TxPR=3–1=2 3 3 2 Timer value 2 1 0 2 1 0 1 0 0 TxCON[6] Timer clock As shown in Figure 6–4, GP Timer Continuous Up-Counting Mode (TxPR = 3 or 2), no clock cycle is missed from the time the counter reaches the period register value to the time it starts another counting cycle.
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General-Purpose (GP) Timers The direction of counting is indicated for the timer in this mode by the corresponding direction indication bit in GPTCONA/B: 1 means counting up; 0 means counting down. Either the external clock from the TCLKINA/B pin or the Internal device clock can be used as the input clock for the timer in this mode. Figure 6–5 shows the directional up-/down-counting mode of the GP timers. Figure 6–5.
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General-Purpose (GP) Timers if the initial value was 0. When the initial value in the timer counter is the same as that of the period register, the timer counts down to 0 and continues again as if the initial value was 0. If the initial value of the timer is between 0 and the contents of the period register, the timer counts up to the period value and continues to finish the period as if the initial counter value was the same as that of the period register.
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General-Purpose (GP) Timers 6.3.2 GP Timer Compare Operation Each GP timer has an associated compare register TxCMPR and a PWM output pin TxPWM. The value of a GP timer counter is constantly compared to that of its associated compare register. A compare match occurs when the value of the timer counter is the same as that of the compare register. Compare operation is enabled by setting TxCON[1] to 1.
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General-Purpose (GP) Timers - toggles on compare match - remains unchanged until the end of the period - resets to 0 at the end of a period on period match, if the new compare value for the following period is not 0 The output is 1 for the whole period, if the compare value is 0 at the beginning of a period. The output does not reset to 0 if the new compare value for the following period is 0. This is important because it allows the generation of PWM pulses of 0% to 100% duty cycle without glitches.
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General-Purpose (GP) Timers - Toggles on the first compare match - Remains unchanged until the second compare match - Toggles on the second compare match - Remains unchanged until the end of the period - Resets to 0 at the end of the period if there is no second compare match, and the new compare value for the following period is not 0 The output is set to 1 at the beginning of a period and remains 1 until the second compare match if the compare value is 0 at the beginning of a period.
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General-Purpose (GP) Timers Output Logic The output logic further conditions the output of the waveform generator to form the ultimate PWM output that controls different kinds of power devices. The PWM output can be specified active high, active low, forced low, and forced high by proper configuration of the appropriate GPTCONA/B bits. The polarity of the PWM output is the same as that of the output of the associated asymmetric/symmetric waveform generator when the PWM output is specified active high.
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General-Purpose (GP) Timers All GP timer PWM outputs are put in the high-impedance state when any of the following events occurs: - GPTCONA/B[6] is set to 0 by software - PDPINTx is pulled low and is not masked - Any reset event occurs - TxCON[1] is set to 0 by software Active/Inactive Time Calculation For the continuous up-counting mode, the value in the compare register represents the elapsed time between the beginning of a period and the occurrence of the first compare match, that is, the length of the
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General-Purpose (GP) Timers 6.3.3 Timer Control Registers (TxCON and GPTCONA/B) The addresses of the GP timer registers are given in Table 6–3 and Table 6–4 on page 6-11. The bit definition of the individual GP timer control registers, TxCON, is shown in Figure 6–9. The bit definition of the overall GP timer control registers, GPTCONA and GPTCONB, are shown in Figure 6–10 (on page 6-33) and Figure 6–11 (on page 6-34), respectively.
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General-Purpose (GP) Timers Bits 10–8 TPS2–TPS0. Input Clock Prescaler. 000 x/1 100 x/16 001 x/2 101 x/32 010 x/4 110 x/64 011 x/8 111 x/128 x = device (CPU) clock frequency Bit 7 Bit 6 T2SWT1. In case of EVA, this bit is T2SWT1. (GP timer 2 start with GP timer 1.) Start GP timer 2 with GP timer 1’s timer enable bit. This bit is reserved in T1CON. T4SWT3. In case of EVB, this bit is T4SWT3. (GP timer 4 start with GP timer 3.) Start GP timer 4 with GP timer 3’s timer enable bit.
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General-Purpose (GP) Timers Bit 1 TECMPR. Timer compare enable. Bit 0 0 Disable timer compare operation. 1 Enable timer compare operation. SELT1PR. In case of EVA, this bit is SELT1PR. (Period register select.) This bit is a reserved bit in T1CON. SELT3PR. In case of EVB, this bit is SELT3PR. (Period register select.) This bit is a reserved bit in T3CON. 0 Use own period register. 1 Use T1PR (in case of EVA) or T3PR (in case of EVB) as period register ignoring own period register.
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General-Purpose (GP) Timers Bits 8–7 Bit 6 T1TOADC. Start ADC with timer 1 event. 00 No event starts ADC. 01 Setting of underflow interrupt flag starts ADC. 10 Setting of period interrupt flag starts ADC. 11 Setting of compare interrupt flag starts ADC. TCOMPOE. Compare output enable. If PDPINTx is active this bit is set to zero. 0 Disable all GP timer compare outputs (all compare outputs are put in the high-impedance state). Enable all GP timer compare outputs. 1 Bits 5–4 Reserved.
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General-Purpose (GP) Timers Bit 13 0 Counting downward 1 Counting upward Bits 12–11 Reserved. Reads return zero; writes have no effect. Bits 10–9 T4TOADC. Start ADC with timer 4 event. Bits 8–7 Bit 6 00 No event starts ADC. 01 Setting of underflow interrupt flag starts ADC. 10 Setting of period interrupt flag starts ADC. 11 Setting of compare interrupt flag starts ADC. T3TOADC. Start ADC with timer 3 event. 00 No event starts ADC. 01 Setting of underflow interrupt flag starts ADC.
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General-Purpose (GP) Timers PWM Operation To generate a PWM output with a GP timer, a continuous up- or up-/downcounting mode can be selected. Edge-triggered or asymmetric PWM waveforms are generated when a continuous-up count mode is selected. Centered or symmetric PWM waveforms are generated when a continuous-up/-down mode is selected. To set up the GP timer for the PWM operation, do the following: - Set up TxPR according to the desired PWM (carrier) period.
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Compare Units 6.4 Compare Units There are three (full) compare units (compare units 1, 2, and 3) in the EVA module and three (full) compare units (compare units 4, 5, and 6) in the EVB module. Each compare unit has two associated PWM outputs. The time base for the compare units is provided by GP timer 1 (for EVA) and by GP timer 2 (for EVB).
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Compare Units The time base for the compare units and the associated PWM circuits is provided by GP timer 1 (for EVA) or GP timer 2 (for EVB), which can be in any of its counting modes when the compare operation is enabled. Transitions occur on the compare outputs. Compare Inputs/Outputs The inputs to a compare unit include: - Control signals from control registers - GP timer 1/3 (T1CNT/T3CNT) and its underflow and period match signals - RESET The output of a compare unit is a compare match signal.
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Compare Units compare unit, if compare is enabled. A peripheral interrupt request is generated by the flag if the interrupt is unmasked. The timing of output transitions, setting of interrupt flags, and generation of interrupt requests are the same as that of the GP timer compare operation. The outputs of the compare units in compare mode are subject to modification by the output logic, dead band units, and the space vector PWM logic.
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Compare Units 6-40 Bit 15 CENABLE. Compare enable. 0 Disable compare operation. All shadowed registers (CMPRx, ACTRA) become transparent. 1 Enable compare operation. Bits14–13 CLD1, CLD0. Compare register CMPRx reload condition. 00 When T1CNT = 0 (that is, on underflow) 01 When T1CNT = 0 or T1CNT = T1PR (that is, on underflow or period match) 10 Immediately 11 Reserved; result is unpredictable. Bit 12 SVENABLE. Space vector PWM mode enable. 0 Disable space vector PWM mode.
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Compare Units Figure 6–14. Compare Control Register B (COMCONB) — Address 7511h 15 14 13 12 11 10 9 8 CENABLE CLD1 CLD0 SVENABLE ACTRLD1 ACTRLD0 FCOMPOE Reserved RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 7–0 Reserved R-0 Note: R = Read access, W = Write access, -0 = value after reset Bit 15 CENABLE. Compare enable. 0 Disable compare operation. All shadowed registers (CMPRx, ACTRB) become transparent. 1 Enable compare operation. Bits14–13 CLD1, CLD0.
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Compare Units Bits 11–10 ACTRLD1, ACTRLD0. Action control register reload condition. 00 When T3CNT = 0 (on underflow) 01 When T3CNT = 0 or T3CNT = T3PR (on underflow or period match) 10 Immediately 11 Reserved Bit 9 FCOMPOE. Compare output enable. Active PDPINTx clears this bit to zero. 0 PWM output pins are in high-impedance state; that is, they are disabled. 1 PWM output pins are not in high-impedance state; that is, they are enabled. Bits 8–0 Reserved. Read returns zero; writes have no effect.
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Compare Units Bits 14–12 D2–D0. Basic space vector bits. Used only in space vector PWM output generation. Bits 11–10 CMP6ACT1–0. Action on compare output pin 6, CMP6. Bits 9–8 Bits 7–6 Bits 5–4 Bits 3–2 Bits 1–0 00 Forced low 01 Active low 10 Active high 11 Forced high CMP5ACT1–0. Action on compare output pin 5, CMP5. 00 Forced low 01 Active low 10 Active high 11 Forced high CMP4ACT1–0. Action on compare output pin 4, CMP4.
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Compare Units Figure 6–16. Compare Action Control Register B (ACTRB) — Address 7513h 15 14 13 12 11 10 9 8 SVRDIR D2 D1 D0 CMP12ACT1 CMP12ACT0 CMP11ACT1 CMP11ACT0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 7 6 5 4 3 2 1 0 CMP9ACT1 CMP9ACT0 CMP8ACT1 CMP8ACT0 CMP7ACT1 CMP7ACT0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 CMP10ACT1 CMP10ACT0 RW-0 Note: RW-0 R = Read access, W = Write access, -0 = value after reset Bit 15 0 Positive (CCW) 1 Negative (CW) Bits 14–12 D2–D0.
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Compare Units Bits 3–2 Bits 1–0 6.4.2 CMP8ACT1–0. Action on compare output pin 8, CMP8. 00 Forced low 01 Active low 10 Active high 11 Forced high CMP7ACT1–0. Action on compare output pin 7, CMP7. 00 Forced low 01 Active low 10 Active high 11 Forced high Compare Unit Interrupts There is a maskable interrupt flag in EVIFRA and EVIFRC for each compare unit. The interrupt flag of a compare unit is set one clock cycle after a compare match, if compare operation is enabled.
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PWM Circuits Associated With Compare Units 6.5 PWM Circuits Associated With Compare Units The PWM circuits associated with compare units make it possible to generate six PWM output channels (per EV) with programmable dead-band and output polarity. The EVA PWM circuits functional block diagram is shown in Figure 6–17.
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PWM Circuits Associated With Compare Units The PWM circuits are designed to minimize CPU overhead and user intervention when generating pulse width modulated waveforms used in motor control and motion control applications. PWM generation with compare units and associated PWM circuits are controlled by the following control registers: T1CON, COMCONA, ACTRA, and DBTCONA (in case of EVA); and T3CON, COMCONB, ACTRB, and DBTCONB (in case of EVB). 6.5.
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PWM Circuits Associated With Compare Units 6.5.2 Programmable Dead-Band (Dead-Time) Unit EVA and EVB have their own programmable dead-band units (DBTCONA and DBTCONB, respectively)The programmable dead-band unit features: - One 16-bit dead-band control register, DBTCONx (RW) - One input clock prescaler: x/1, x/2, x/4, etc.
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PWM Circuits Associated With Compare Units Bit 5 EDBT1. Dead-band timer 1 enable (for pins PWM1 and PWM2 of Compare Unit 1). Bits 4–2 0 Disable 1 Enable DBTPS2 to DBTPS0. Dead-band timer prescaler. 000 x/1 001 x/2 010 x/4 011 x/8 100 x/16 101 x/32 110 x/32 111 x/32 x = Device (CPU) clock frequency Bits 1–0 Reserved. Reads return zero; writes have no effect. Figure 6–19.
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PWM Circuits Associated With Compare Units Bit 5 Bits 4–2 EDBT1. Dead-band timer 1 enable (for pins PWM7 and PWM8 of Compare Unit 4). 0 Disable 1 Enable DBTPS2 to DBTPS0. Dead-band timer prescaler. 000 x/1 001 x/2 010 x/4 011 x/8 100 x/16 101 x/32 110 x/32 111 x/32 x = Device (CPU) clock frequency Bits 1–0 Reserved. Reads return zero; writes have no effect.
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PWM Circuits Associated With Compare Units Table 6–13. Dead-Band Generation Examples DBTPS2–DBTPS0 (p) (DBTCONx[4–2]) DBT3–DBT0 (m) (DBTCONx[11–8]) Note: 110 and 1x1 (P=32) 100 (P=16) 011 (P=8) 010 (P=4) 001 (P=2) 000 (P=1) 0 0 0 0 0 0 0 1 1.6 0.8 0.4 0.2 0.1 0.05 2 3.2 1.6 0.8 0.4 0.2 0.1 3 4.8 2.4 1.2 0.6 0.3 0.15 4 6.4 3.2 1.6 0.8 0.4 0.2 5 8 4 2 1 0.5 0.25 6 9.6 4.8 2.4 1.2 0.6 0.3 7 11.2 5.6 2.8 1.4 0.7 0.35 8 12.8 6.4 3.2 1.6 0.
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PWM Circuits Associated With Compare Units Figure 6–20.
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PWM Circuits Associated With Compare Units Other Important Features of Dead-Band Units The dead-band unit is designed to prevent an overlap under any operating situation between the turn-on period of the upper and lower devices controlled by the two PWM outputs associated with each compare unit. This includes situations when the user has loaded a dead-band value greater than that of the duty cycle, and when the duty cycle is 100% or 0%.
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PWM Circuits Associated With Compare Units Figure 6–21. Output Logic Block Diagram (x = 1, 2, or 3; y = 1, 2, 3, 4, 5, or 6) ACTR[0–1, 2–3, . . .
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PWM Waveform Generation With Compare Units and PWM Circuits 6.6 PWM Waveform Generation With Compare Units and PWM Circuits A pulse width modulated (PWM) signal is a sequence of pulses with changing pulse widths. The pulses are spread over a number of fixed-length periods so that there is one pulse in each period. The fixed period is called the PWM (carrier) period and its inverse is called the PWM (carrier) frequency.
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PWM Waveform Generation With Compare Units and PWM Circuits 6.6.1 Generation of PWM Outputs With Event Manager Each of the three compare units, together with GP timer 1 (in case of EVA) or GP timer 3 (in case of EVB), the dead-band unit, and the output logic in the event manager module, can be used to generate a pair of PWM outputs with programmable dead-band and output polarity on two dedicated device pins.
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PWM Waveform Generation With Compare Units and PWM Circuits 6.6.3 Asymmetric PWM Waveform Generation The edge-triggered or asymmetric PWM signal is characterized by modulated pulses which are not centered with respect to the PWM period, as shown in Figure 6–22. The width of each pulse can only be changed from one side of the pulse. Figure 6–22.
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PWM Waveform Generation With Compare Units and PWM Circuits After GP timer 1 (or GP timer 3) is started, the compare registers are rewritten every PWM period with newly determined compare values to adjust the width (the duty cycle) of PWM outputs that control the switch-on and off duration of the power devices. Since the compare registers are shadowed, a new value can be written to them at any time during a period.
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PWM Waveform Generation With Compare Units and PWM Circuits There are usually two compare matches in a PWM period in symmetric PWM waveform generation, one during the upward counting before period match, and another during downward counting after period match. A new compare value becomes effective after the period match (reload on period) because itmakes it possible to advance or delay the second edge of a PWM pulse.
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Space Vector PWM 6.7 Space Vector PWM Space vector PWM refers to a special switching scheme of the six power transistors of a 3-phase power converter. It generates minimum harmonic distortion to the currents in the windings of a 3-phase AC motor. It also provides more efficient use of supply voltage in comparison with the sinusoidal modulation method. 6.7.
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Space Vector PWM Table 6–14.
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Space Vector PWM Figure 6–25. Basic Space Vectors and Switching Patterns CCW direction (SVRDIR=0) U120 (010) U60 (011) Uout T2 U380 (110) T1 U140 (100) U0 (001) U300 (101) CW direction (SVRDIR=1) The binary representations of two adjacent basic vectors are different in only one bit. That is, only one of the upper transistors switches when the switching pattern switches from Ux to Ux+60 or from Ux+60 to Ux. Also, the zero vectors O000 and O111 apply no voltage to the motor.
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Space Vector PWM Software To generate space vector PWM outputs, the user software must: - Configure ACTRx to define the polarity of the compare output pins - Configure COMCONx to enable compare operation and space vector PWM mode, and set the reload condition for CMPRx to be underflow - Put GP timer 1 (or GP timer 3) in continuous up-/down-counting mode to start the operation The user software then needs to determine the voltage Uout to be applied to the motor phases in the two dimensional d-q plane, dec
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Space Vector PWM Space Vector PWM Waveforms The space vector PWM waveforms generated are symmetric with respect to the middle of each PWM period, and for this reason, it is called the symmetric space vector PWM generation method. Figure 6–26 shows examples of the symmetric space vector PWM waveforms. The Unused Compare Register Only two compare registers are used in space vector PWM output generation. The third compare register, however, is still constantly compared with GP timer 1.
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Space Vector PWM Figure 6–26.
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Capture Units 6.8 Capture Units Capture units enable logging of transitions on capture input pins. There are six capture units, three is each EV module. Capture Units 1, 2, and 3 are associated with EVA and Capture Units 4, 5, and 6 are associated with EVB. Each capture unit is associated with a capture input pin. Each EVA capture unit can choose GP timer 2 or 1 as its time base; however, CAP1 and CAP2 cannot choose a different timer between themselves as their timebase.
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Capture Units Figure 6–27. Capture Units Block Diagram (EVA) T2CNT GP timer 2 counter CAPCONA[9,10] 2 T1CNT GP timer 1 counter MUX CAPCONA[12–14] 16 16 2-level FIFO RS stacks EN Edge detect RS 3 CAP1,2,3 Capture unit 3 cap.
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Capture Units Figure 6–28. Capture Units Block Diagram (EVB) T2CNT GP timer 4 counter CAPCONB[9,10] 2 T1CNT GP timer 3 counter MUX CAPCONB[12–14] 16 16 2-level FIFO RS stacks EN Edge detect RS 3 CAP4,5,6 Capture unit 6 cap. event Edge 6 select CAPCONB[8] CAPCONB[2–7] ADC start 8 CAPCONB[15] Cap FIFO status clear 6 CAPFIFOB[13–15] 6.8.
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Capture Units - Three 16-bit 2-level-deep FIFO stacks, one for each capture unit. - Six Schmitt-triggered capture input pins, CAP1 through CAP6, one input pin for each capture unit. (All inputs are synchronized with the device/CPU clock: in order for a transition to be captured, the input must hold at its current level to meet the two rising edges of the device clock.
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Capture Units Capture Unit Setup For a capture unit to function properly, the following register setup must be performed: 1) Initialize the CAPFIFOx and clear the appropriate status bits. 2) Set the selected GP timer in one of its operating modes. 3) Set the associated GP timer compare register or GP timer period register, if necessary. 4) Set up CAPCONA or CAPCONB as appropriate. 6.8.
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Capture Units Bits 14–13 CAPQEPN. Capture Units 1 and 2 and QEP circuit control. 00 Bit 12 01 Disable Capture Units 1 and 2 and QEP circuit. FIFO stacks retain their contents. Enable Capture Units 1 and 2, disable QEP circuit. 10 Reserved 11 Enable QEP circuit. Disable Capture Units 1 and 2; bits 4–7 and 9 are ignored. CAP3EN. Capture Unit 3 control. 0 1 Disable Capture Unit 3; FIFO stack of Capture Unit 3 retains its contents. Enable Capture Unit 3 Bit 11 Reserved.
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Capture Units Bits 3–2 CAP3EDGE. Edge detection control for Capture Unit 3. Bits 1–0 00 No detection 01 Detect rising edge 10 Detect falling edge 11 Detect both edges Reserved. Reads return zero; writes have no effect. Capture Control Register B (CAPCONB) Figure 6–30.
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Capture Units Bit 11 Reserved. Reads return zero; writes have no effect. Bit 10 CAP6TSEL. GP timer selection for Capture Unit 6. Bit 9 Bit 8 Bits 7–6 Bits 5–4 Bits 3–2 Bits 1–0 0 Select GP timer 5 1 Select GP timer 4 CAP45TSEL. GP timer selection for Capture Units 4 and 5. 0 Select GP timer 5 1 Select GP timer 4 CAP6TOADC. Capture Unit 6 event starts ADC. 0 No action 1 Start ADC when the CAP6INT flag is set CAP4EDGE. Edge detection control for Capture Unit 4.
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Capture Units Figure 6–31. Capture FIFO Status Register A (CAPFIFOA) — Address 7422h 15–14 13–12 11–10 9–8 Reserved CAP3FIFO CAP2FIFO CAP1FIFO R-0 RW-0 RW-0 RW-0 7–0 Reserved R-0 Note: R = Read access, W = Write access, -0 = value after reset Bits 15–14 Reserved. Reads return zero; writes have no effect. Bits 13–12 CAP3FIFO. CAP3FIFO Status.
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Capture Units Figure 6–32. Capture FIFO Status Register B (CAPFIFOB) — Address 7522h 15–14 13–12 11–10 9–8 Reserved CAP6FIFO CAP5FIFO CAP4FIFO R-0 RW-0 RW-0 RW-0 7–0 Reserved R-0 Note: R = Read access, W = Write access, -0 = value after reset Bits 15–14 Reserved. Reads return zero; writes have no effect. Bits 13–12 CAP6FIFO. CAP6FIFO Status. Bits 11–10 Bits 9–8 Bits 7–0 6.8.
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Capture Units CAP4FBOT, CAP5FBOT, and CAP6FBOT (in case of EVB). The top-level register of any of the FIFO stacks is a read-only register that always contains the oldest counter value captured by the corresponding capture unit. Therefore, a read access to the FIFO stack of a capture unit always returns the oldest counter value stored in the stack.
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Capture Units 6.8.5 Capture Interrupt When a capture is made by a capture unit and there is already at least one valid value in the FIFO (indicated by CAPxFIFO bits not equal to zero), the corresponding interrupt flag is set, and if unmasked, a peripheral interrupt request is generated. Thus, a pair of captured counter values can be read by an interrupt service routine if the interrupt is used.
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Quadrature Encoder Pulse (QEP) Circuit 6.9 Quadrature Encoder Pulse (QEP) Circuit Each Event Manager module has a quadrature encoder pulse (QEP) circuit. The QEP circuit, when enabled, decodes and counts the quadrature encoded input pulses on pins CAP1/QEP1 and CAP2/QEP2 (in case of EVA) or CAP4/QEP3 and CAP5/QEP4 (in case of EVB). The QEP circuit can be used to interface with an optical encoder to get position and speed information from a rotating machine.
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Quadrature Encoder Pulse (QEP) Circuit Figure 6–34. Quadrature Encoder Pulse (QEP) Circuit Block Diagram for EVB GPT4 clock GP timer 4 CLKIN M U X Prescaler T4CON[8,9,10] 2 CAPCONB[13,14] T4CON[4,5] 2 GPT4 dir M U X CLKOUT TDIRB 2 CLK DIR QEP decoder logic 2 M U X 2 CAP4/QEP3 CAP5/QEP4 2 Capture unit 4,5 6.9.3 Decoding Quadrature encoded pulses are two sequences of pulses with a variable frequency and a fixed phase shift of a quarter of a period (90 degrees).
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Quadrature Encoder Pulse (QEP) Circuit Quadrature Encoded Pulse Decoding Example Figure 6–35 shows an example of quadrature encoded pulses and the derived clock and counting direction. Figure 6–35. Quadrature Encoded Pulses and Decoded Timer Clock and Direction QEP0 QEP1 Quadrature CLK DIR 6.9.4 QEP Counting GP timer 2 (or 4) always starts counting from its current value. A desired value can be loaded to the GP timer’s counter prior to enabling the QEP mode.
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Quadrature Encoder Pulse (QEP) Circuit To start the operation of the QEP circuit in EVB: 1) Load GP timer 4’s counter, period, and compare registers with desired values, if necessary. 2) Configure T4CON to set GP timer 4 in directional-up/down mode with the QEP circuits as clock source, and enable the selected timer. 3) Configure CAPCONB to enable the QEP circuit.
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Event Manager (EV) Interrupts 6.10 Event Manager (EV) Interrupts EV interrupt events are organized into 3 groups: A, B, and C. Each group is associated with a different interrupt flag and interrupt enable register. There are several event manager peripheral interrupt requests in each EV interrupt group. Table 6–16 shows all EVA interrupts, their priority, and grouping; and Table 6–17 shows all EVB interrupts, their priority, and grouping.
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Event Manager (EV) Interrupts Table 6–16.
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Event Manager (EV) Interrupts Table 6–17.
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Event Manager (EV) Interrupts Interrupt Vector The peripheral interrupt vector corresponding to the interrupt flag that has the highest priority among the flags that are set and enabled is loaded into the PIVR when an interrupt request is acknowledged (this is all done in the peripheral interrupt controller, external to the event manager peripheral). Failure to Clear the Interrupt Flag Bit The interrupt flag bit in the peripheral register must be cleared by software writing a 1 to the bit in the ISR.
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Event Manager (EV) Interrupts Bits 15–11 Reserved. Reads return zero; writes have no effect. Bit 10 T1OFINT FLAG. GP timer 1 overflow interrupt. Read: 0 1 Write: 0 1 Bit 9 1 Write: 0 1 1 Write: 0 1 Flag is reset Flag is set No effect Reset flag Flag is reset Flag is set No effect Reset flag T1PINT FLAG. GP timer 1 period interrupt. Read: 0 1 Write: 0 1 Flag is reset Flag is set No effect Reset flag Bits 6–4 Reserved. Reads return zero; writes have no effect. Bit 3 CMP3INT FLAG.
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Event Manager (EV) Interrupts Bit 1 CMP1INT FLAG. Compare 1 interrupt. Read: 0 1 Write: 0 1 Bit 0 Flag is reset Flag is set No effect Reset flag PDPINTA FLAG. Power drive protection interrupt. Read: 0 1 Write: 0 1 Flag is reset Flag is set No effect Reset flag EVA Interrupt Flag Register B (EVAIFRB) Figure 6–37.
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Event Manager (EV) Interrupts Bit 0 T2PINT FLAG. GP timer 2 period interrupt. Read: 0 1 Write: 0 1 Flag is reset Flag is set No effect Reset flag EVA Interrupt Flag Register C (EVAIFRC) Figure 6–38. EVA Interrupt Flag Register C (EVAIFRC) — Address 7431h ÍÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍ 15–3 Reserved R-0 Note: 1 0 CAP3INT FLAG CAP2INT FLAG CAP1INT FLAG RW-0 RW-0 RW-0 R = Read access, W = Write access, -0 = value after reset Bits 15–3 Reserved.
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Event Manager (EV) Interrupts EVA Interrupt Mask Register A (EVAIMRA) Figure 6–39.
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Event Manager (EV) Interrupts Bit 0 PDPINTA ENABLE. This is enabled (set to 1) following reset. 0 Disable 1 Enable EVA Interrupt Mask Register B (EVAIMRB) Figure 6–40. EVA Interrupt Mask Register B (EVAIMRB) — Address 742Dh ÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍ ÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍ ÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍ 15–4 Reserved R-0 Note: 3 2 1 0 T2OFINT ENABLE T2UFINT ENABLE T2CINT ENABLE T2PINT ENABLE RW-0 RW-0 RW-0 RW-0 R = Read access, W = Write access, -0 = value after reset Bits 15–4 Reserved.
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Event Manager (EV) Interrupts Bits 15–3 Reserved. Reads return zero; writes have no effect. Bit 2 CAP3INT ENABLE Bit 1 Bit 0 0 Disable 1 Enable CAP2INT ENABLE 0 Disable 1 Enable CAP1INT ENABLE 0 Disable 1 Enable EVB Interrupt Flag Register A (EVBIFRA) Figure 6–42.
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Event Manager (EV) Interrupts Bit 8 T3CINT FLAG. GP timer 3 compare interrupt. Read: 0 1 Write: 0 1 Bit 7 Flag is set No effect Reset flag T3PINT FLAG. GP timer 3 period interrupt. Read: 0 1 Write: 0 1 Flag is reset Flag is set No effect Reset flag Bits 6–4 Reserved. Reads return zero; writes have no effect. Bit 3 CMP6INT FLAG. Compare 6 interrupt. Read: 0 1 Write: 0 1 Bit 2 1 Write: 0 1 Bit 1 Flag is set No effect Reset flag Flag is reset Flag is set No effect Reset flag CMP4INT FLAG.
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Event Manager (EV) Interrupts EVB Interrupt Flag Register B (EVBIFRB) Figure 6–43. EVB Interrupt Flag Register B (EVBIFRB) — Address 7530h ÍÍÍÍÍ ÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍÍ 15–4 Reserved R-0 Note: 3 2 1 0 T4OFINT FLAG T4UFINT FLAG T4CINT FLAG T4PINT FLAG RW-0 RW-0 RW-0 RW-0 R = Read access, W = Write access, -0 = value after reset Bits 15–4 Reserved. Reads return zero; writes have no effect. Bit 3 T4OFINT FLAG. GP timer 4 overflow interrupt.
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Event Manager (EV) Interrupts EVB Interrupt Flag Register C (EVBIFRC) Figure 6–44. EVB Interrupt Flag Register C (EVBIFRC) — Address 7531h ÍÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍ 15–3 Reserved R-0 Note: 1 0 CAP6INT FLAG CAP5INT FLAG CAP4INT FLAG RW-0 RW-0 RW-0 R = Read access, W = Write access, -0 = value after reset Bits 15–3 Reserved. Reads return zero; writes have no effect. Bit 2 CAP6INT FLAG. Capture 6 interrupt.
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Event Manager (EV) Interrupts EVB Interrupt Mask Register A (EVBIMRA) Figure 6–45.
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Event Manager (EV) Interrupts Bit 0 PDPINTB ENABLE. This is enabled (set to 1) following reset. 0 Disable 1 Enable EVB Interrupt Mask Register B (EVBIMRB) Figure 6–46. EVB Interrupt Mask Register B (EVBIMRB) — Address 752Dh ÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍ ÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍ ÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍÍ ÍÍÍÍ 15–4 Reserved R-0 Note: 3 2 1 0 T4OFINT ENABLE T4UFINT ENABLE T4CINT ENABLE T4PINT ENABLE RW-0 RW-0 RW-0 RW-0 R = Read access, W = Write access, -0 = value after reset Bits 15–4 Reserved.
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Event Manager (EV) Interrupts Bits 15–3 Reserved. Reads return zero; writes have no effect.
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Chapter 7 Analog-to-Digital Converter (ADC) Topic Page 7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.2 ADC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.3 ADC Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 7.4 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Features 7.1 Features - 10-bit ADC core with built-in Sample and Hold (S/H) - Fast conversion time (S/H + Conversion) of 500 ns - Sixteen multiplexed analog inputs (ADCIN0 – ADCIN15). Eight in ’2402 - Autosequencing capability – up to 16 “autoconversions” in a single ses- sion. Each conversion session can be programmed to select any one of the 16 input channels.
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Features Table 7–1.
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ADC Overview 7.2 ADC Overview 7.2.1 Autoconversion Sequencer: Principle of Operation The ADC sequencer consists of two independent 8-state sequencers (SEQ1 and SEQ2) that can also be cascaded together to form one 16-state sequencer (SEQ). The word “state” represents the number of autoconversions that can be performed with the sequencer. Block diagrams of the single (16-state, cascaded) and dual (two 8-state, separated) sequencer modes are shown in Figure 7–1 and Figure 7–2, respectively.
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ADC Overview Figure 7–1.
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ADC Overview Figure 7–2.
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ADC Overview The sequencer operation for both 8-state and 16-state modes is almost identical; the few differences are highlighted in Table 7–2. Table 7–2.
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ADC Overview stored in one of the eight result registers (RESULT0 – RESULT7 for SEQ1 and RESULT8 – RESULT15 for SEQ2). These registers are filled from the lowest address to the highest address. The number of conversions in a sequence is controlled by MAX_CONVn (a 3-bit or 4-bit field in the MAX_CONV register), which is automatically loaded into the Sequencing Counter Status bits (SEQ_CNTR3 – 0) in the Autosequence Status Register (AUTO_SEQ_SR) at the start of an autosequenced conversion session.
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ADC Overview - If CONT_RUN is not set, the sequencer stays in the last state (CONV06, in this example) and SEQ_CNTR_n continues to hold a value of zero. Since the interrupt flag is set every time SEQ_CNTR_n reaches zero, the user can (if needed) manually reset the sequencer (using the RST_SEQn bit in the ADCTRL2 register) in the Interrupt Service Routine (ISR), so that SEQ_CNTR_n gets reloaded with the original value in MAX_CONV1 and SEQ1 state is set to CONV00.
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ADC Overview Figure 7–3. Example of Event Manager Triggers to Start the Sequencer 50 µs 25 µs EV1 Timer 1 Counter EV1 PWM I1,I2,I3 V1,V2,V3 I1,I2,I3 V1,V2,V3 Here MAX_CONV1 is set to 2 and the ADC Input Channel Select Sequencing Control Registers (CHSELSEQn) are set to: Bits 15–12 Bits 11–8 Bits 7–4 Bits 3–0 70A3h V1 I3 I2 I1 CHSELSEQ1 70A4h x x V3 V2 CHSELSEQ2 70A5h x x x x CHSELSEQ3 70A6h x x x x CHSELSEQ4 Once reset and initialized, SEQ1 waits for a trigger.
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ADC Overview At the end of the second autoconversion session, the ADC result registers will have following values: Buffer Register ADC conversion result buffer RESULT0 I1 RESULT1 I2 RESULT2 I3 RESULT3 V1 RESULT4 V2 RESULT5 V3 RESULT6 x RESULT7 x RESULT8 x RESULT9 x RESULT10 x RESULT11 x RESULT12 x RESULT13 x RESULT14 x RESULT15 x At this point, SEQ1 keeps “waiting” at the current state for another trigger.
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ADC Overview 7.2.4 Input Trigger Description Each sequencer has a set of trigger inputs that can be enabled/disabled.
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ADC Overview Case 1: Number of samples in the first and second sequences are not equal - Mode 1 Interrupt operation (i.e., Interrupt request occurs at every EOS) 1) Sequencer is initialized with MAX_CONVn = 1 for converting I1 and I2 2) At ISR “a”, MAX_CONVn is changed to 2 (by software) for converting V1, V2, and V3 3) At ISR “b”, the following events take place : 1) MAX_CONVn is changed to 1 again for converting I1 and I2. 2) Values I1, I2, V1, V2, and V3 are read from ADC result registers.
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ADC Overview Case 3: Number of samples in the first and second sequences are equal (with dummy read) - Mode 2 Interrupt operation (i.e., Interrupt request occurs at every other EOS) 1) Sequencer is initialized with MAX_CONVn = 2 for I1, I2, x sampling 2) At ISR “b” and “d”, the following events take place : 1) Values I1, I2, x,V1, V2, and V3 are read from ADC result registers. 2) The sequencer is reset. 3) Step 2 is repeated.
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ADC Overview Figure 7–4.
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ADC Clock Prescaler 7.3 ADC Clock Prescaler The S/H block in the ’240x ADC can be tailored to accomodate the variation in source impedances. This is achieved by the ACQ_PS3–ACQ_PS0 bits and the CPS bit in the ADCTR1 register. The analog-to-digital conversion process can be divided into two time segments, as shown in Figure 7–5. Figure 7–5.
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ADC Clock Prescaler Figure 7–6.
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Calibration 7.4 Calibration In the calibration mode, the sequencers are not operational and the ADCINn pins are not connected to the A/D converter. The signal that gets connected to the A/D converter input is determined by BRG_ENA (Bridge Enable) and HI/LO (VREFHI/VREFLO selection) bits. These two signals connect either VREFLO or VREFHI or their midpoint to the A/D converter input and a single conversion is then done.
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Self-Test 7.5 Self-Test The self-test mode is a way to detect shorts/opens on an ADC pin. The sampling period is doubled in this mode. In the first half of the sampling period, either VREFHI or VREFLO (as determined by the HI/LO bit) is connected to the input of the A/D converter, in addition to the analog input signal provided by the user. In the second half of the sampling period, only user signal is connected to the ADC.
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Register Bit Descriptions 7.6 Register Bit Descriptions 7.6.1 ADC Control Register 1 Figure 7–7.
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Register Bit Descriptions Bits 11–8 ACQ_PS3 – ACQ_PS0. Acquisition time window – prescale bits 3–0 These bits define the ADC clock prescale factor applied to the acquisition portion of the conversion.
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Register Bit Descriptions quence is active. This bit will take effect at the end of the current conversion sequence; i.e., software can set/clear this bit until EOS has occurred, for valid action to be taken. In the continuous conversion mode, there is no need to reset the sequencer; however, the sequencer must be reset in the start-stop mode to put the converter in state CONV00. 0 1 Bit 5 Bit 4 Start-stop mode. Sequencer stops after reaching EOS. This is used for multiple time-sequenced triggers.
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Register Bit Descriptions Bit 1 HI/LO. VREFHI / VREFLO selection When the fail self-test mode is enabled (STEST_ENA = 1), HI/LO defines the test voltage to be connected. In calibration mode, HI/LO defines the reference source polarity; see Table 7–3. In normal operating mode, HI/LO has no effect. 0 VREFLO is used as precharge value at ADC input 1 VREFHI is used as precharge value at ADC input Table 7–3.
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Register Bit Descriptions Bit 14 RST_SEQ1 / STRT_CAL. Reset Sequencer/Start Calibration Case: Calibration Disabled (Bit 3 of ADCTRL1) = 0 Writing a 1 to this bit will reset the sequencer immediately to an initial “pretriggered” state, i.e., waiting for a trigger at CONV00. A currently active conversion sequence will be aborted. 0 No action 1 Immediately reset sequencer to state CONV00 Case: Calibration Enabled (Bit 3 of ADCTRL1) = 1 Writing a 1 to this bit will begin the converter calibration process.
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Register Bit Descriptions Bit 12 SEQ1_BSY. SEQ1 Busy This bit is set to a 1 while the ADC autoconversion sequence is in progress. It is cleared when the conversion sequence is complete. Bits 11–10 Bit 9 0 Sequencer is Idle (i.e., waiting for trigger). 1 Conversion sequence is in progress. INT_ENA_SEQ1.
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Register Bit Descriptions Bit 5 SOC_SEQ2. Start-of-conversion trigger for Sequencer 2 (SEQ2) (Only applicable in dual-sequencer mode, ignored in cascaded mode.) This bit can be set by the following triggers: - S/W – Software writing of 1 to this bit - EVB – Event Manager B When a trigger occurs, there are 3 possibilities: Case 1: SEQ2 idle and SOC bit clear SEQ2 starts immediately (under arbiter control) and the bit is cleared, allowing for any “pending” trigger requests.
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Register Bit Descriptions Bit 1 INT_FLAG_SEQ2. ADC interrupt flag bit for SEQ2 This bit indicates whether an interrupt event has occurred or not. This bit must be cleared by the user writing a 1 to it. Bit 0 7.6.3 0 No interrupt event. 1 An interrupt event has occurred. EVB_SOC_SEQ2. Event Manager B SOC mask bit for SEQ2 0 SEQ2 cannot be started by EVB trigger. 1 Allows SEQ2 to be started by Event Manager B trigger. The Event Manager can be programmed to start a conversion on various events.
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Register Bit Descriptions This register contains the number of conversions executed during an autoconversion session. An autoconversion session always starts with the “initial state” and continues sequentially until the “end state” if allowed. The result buffer is filled in a sequential order. Any number of conversions between 1 and (MAX_CONVn +1) can be programmed for a session, - For SEQ1 operation, bits MAX_CONV1_2 – 0 are used. - For SEQ2 operation, bits MAX_CONV2_2 – 0 are used.
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Register Bit Descriptions Table 7–4. Bit Selections for MAX_CONV1 for Various Number of Conversions 7.6.4 MAX_CONV1.3–0 Number of conversions 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16 Autosequence Status Register Figure 7–10.
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Register Bit Descriptions SEQ2 is irrelevant in cascaded mode. At the start of an autosequenced session, SEQ_CNTR_n is loaded with the value from MAX_CONVn. The SEQ_CNTR_n bits can be read at any time during the countdown process to check status of the sequencer. This value, together with the SEQ1 and SEQ2 Busy bits, uniquely identifies the progress or state of the active sequencer at any point in time. Table 7–5.
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Register Bit Descriptions 7.6.5 ADC Input Channel Select Sequencing Control Registers Figure 7–11.
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Register Bit Descriptions Table 7–6.
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Register Bit Descriptions 7.6.6 ADC Conversion Result Buffer Registers (for Dual-Sequencer Mode) RESULT15 Note: 8th Conv (Seq 2) 16th Conv In the cascaded sequencer mode, registers RESULT8 through RESULT15 will hold the results of the ninth through fifteenth conversions. Figure 7–12. ADC Conversion Result Buffer Registers 15 14 13 12 11 10 9 8 D9 D8 D7 D6 D5 D4 D3 D2 7 6 5 4 3 2 1 0 D1 D0 0 0 0 0 0 0 Notes: 1) Buffer addresses = 70A8h to 70B7h (i.e.
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ADC Conversion Clock Cycles 7.7 ADC Conversion Clock Cycles The conversion time is a function of the number of conversions performed in a given sequence. The conversion cycle can be divided into five phases: - Start of Sequence Sync-up (SOS_synch) The SOS_synch applies only to the first conversion in a sequence.
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ADC Conversion Clock Cycles Example 7–4. Calculating the Conversion Time for a Multiple Conversion Sequence With CPS = 0 and ACQ = 0: 1st conversion – 15 CLKOUT cycles 2nd conversion – 13 CLKOUT cycles 3rd conversion – 13 CLKOUT cycles Last conversion – 14 CLKOUT cycles. Example 7–5. Calculating the Conversion Time for a Single Conversion Sequence With CPS = 1 and ACQ = 1: 1st and only conversion – 33 or 34 CLKOUT cycles.
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Chapter 8 Serial Communications Interface (SCI) This chapter describes the architecture, functions, and programming of the serial communications interface (SCI) module. All registers in this peripheral are eight bits wide. The programmable SCI supports asynchronous serial (UART) digital communications between the CPU and other asynchronous peripherals that use the standard NRZ (non-return-to-zero) format.
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Differences vs. ’C240 SCI 8.1 Differences vs. ’C240 SCI Multiplexing the SCI pins with general-purpose I/O is controlled by bits in the digital I/O peripheral. As a consequence, the register SCIPC2 (705Eh) has been removed. The CLKENA bit in SCICTL1 (7051h) has been removed, since it served no purpose in 2-pin SCI implementations. The function of the SCIENA bit in SCICCR (7050h) has changed, and is now a LOOP BACK ENA test mode bit.
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Differences vs.
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Differences vs. ’C240 SCI Figure 8–1. SCI Block Diagram SCITXBUF.7–0 Frame format and mode SCICTL1.3 Parity Even/odd Enable SCICCR.6 SCICCR.5 Transmitter data buffer register 1 SCI TX interrupt TXRDY TXINTENA SCICTL2.7 External connections SCICTL2.0 TXEMPTY 8 TXINT SCICTL2.6 WUT TXSHF register TXENA SCITXD SCICTL1.1 SCIHBAUD.15–8 SCI priority level 1 Low INT priority Baud rate MSbyte register SCI clock High INT priority 0 SCILBAUD.7–0 SCITX priority SCIPRI.
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Differences vs. ’C240 SCI 8.1.2 Architecture The major elements used in full duplex are shown in Figure 8–1, SCI Block Diagram and include: - A transmitter (TX) and its major registers (upper half of Figure 8–1) J SCITXBUF — transmitter data buffer register. Contains data (loaded by the CPU) to be transmitted J TXSHF register — transmitter shift register.
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Differences vs. ’C240 SCI 8.1.3 SCI Module Registers Table 8–1. Addresses of SCI Registers Described In Section Page Defines the character format, protocol, and communications mode used by the SCI. 8.6.1 8-20 SCI control register 1 Controls the RX/TX and receiver error interrupt enable, TXWAKE and SLEEP functions, and the SCI software reset. 8.6.2 8-22 SCIHBAUD SCI baud register, high bits Stores the data (MSbyte) required to generate the bit rate. 8.6.
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Differences vs. ’C240 SCI 8.1.4 Multiprocessor and Asynchronous Communication Modes The SCI has two multiprocessor protocols, the idle-line multiprocessor mode (see section 8.3.1 on page 8-10) and the address-bit multiprocessor mode (see section 8.3.2 on page 8-12). These protocols allow efficient data transfer between multiple processors. The SCI offers the universal asynchronous receiver/transmitter (UART) communications mode for interfacing with many popular peripherals.
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SCI Programmable Data Format 8.2 SCI Programmable Data Format SCI data, both receive and transmit, is in NRZ (nonreturn-to-zero) format. The NRZ data format, shown in Figure 8–2, consists of: - one start bit - one to eight data bits - an even/odd parity bit (optional) - one or two stop bits - an extra bit to distinguish addresses from data (address-bit mode only) The basic unit of data is called a character and is one to eight bits in length.
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SCI Multiprocessor Communication 8.3 SCI Multiprocessor Communication The multiprocessor communication format allows one processor to efficiently send blocks of data to other processors on the same serial link. On one serial line, there should be only one transfer at a time. In other words, there can be only one talker on a serial line at a time. The first byte of a block of information that the talker sends contains an address byte that is read by all listeners.
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SCI Multiprocessor Communication In both multiprocessor modes, the receipt sequence is: 1) At the receipt of an address block, the SCI port wakes up and requests an interrupt (bit RX/BK INT ENA-SCICTL2.1 must be enabled to request an interrupt). It reads the first frame of the block, which contains the destination address. 2) A software routine is entered through the interrupt and checks the incoming address. This address byte is checked against its device address byte stored in memory.
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SCI Multiprocessor Communication The steps followed by the idle-line mode: 1) SCI wakes up after receipt of the block-start signal. 2) The processor now recognizes the next SCI interrupt. 3) The service routine compares the received address (sent by a remote transmitter) to its own. 4) If the CPU is being addressed, the service routine clears the SLEEP bit and receives the rest of the data block. 5) If the CPU is not being addressed, the SLEEP bit remains set.
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SCI Multiprocessor Communication To send out a block start signal of exactly one frame time during a sequence of block transmissions: 1) Write a 1 to the TXWAKE bit. 2) Write a data word (content not important: a don’t care) to the SCITXBUF register (transmit data buffer) to send a block-start signal. (The first data word written is suppressed while the block-start signal is sent out and ignored after that.
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SCI Multiprocessor Communication 3) Since TXSHF and WUT are both double-buffered, SCITXBUF and TXWAKE can be written to immediately after TXSHF and WUT are loaded. 4) To transmit non-address frames in the block, leave the TXWAKE bit set to 0. Note: Address-bit format for transfers of 11 bytes or less As a general rule, the address-bit format is typically used for data frames of 11 bytes or less. This format adds one bit value (1 for an address frame, 0 for a data frame) to all data bytes transmitted.
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SCI Communication Format 8.4 SCI Communication Format The SCI asynchronous communication format uses either single line (one way) or two line (two way) communications. In this mode, the frame consists of a start bit, one to eight data bits, an optional even/odd parity bit, and one or two stop bits (shown in Figure 8–6). There are eight SCICLK periods per data bit. The receiver begins operation on receipt of a valid start bit.
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SCI Communication Format Figure 8–7. SCI RX Signals in Communication Modes RXENA 1 6 RXRDY 3 4 2 SCIRXD pin 5 Start 0 1 2 3 4 5 Ad Pa Stop Start 0 1 2 Frame Notes: 1) Flag bit RXENA (SCICTL1.0) goes high to enable the receiver. 2) Data arrives on the SCIRXD pin, start bit detected. 3) Data is shifted from RXSHF to the receive buffer register (SCIRXBUF); an interrupt is requested. Flag bit RXRDY (SCIRXST.6) goes high to signal that a new character has been received.
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SCI Communication Format Figure 8–8. SCI TX Signals in Communications Modes TXENA 1 6 TXRDY 2 3 4 5 TX EMPTY First Character SCITXD pin Start 0 1 2 Ad Second Character Pa Stop Start 0 Frame Notes: 1 2 Ad 7 Pa Stop Frame 1) Bit TXENA (SCICTL1.1) goes high, enabling the transmitter to send data. 2) SCITXBUF is written to; thus, (1) the transmitter is no longer empty, and (2) TXRDY goes low. 3) The SCI transfers data to the shift register (TXSHF).
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SCI Port Interrupts 8.5 SCI Port Interrupts The internally-generated serial clock is determined by the device clock frequency and the baud-select registers. The SCI uses the 16-bit value of the baud-select registers to select one of 64k different serial clock rates. The SCI’s receiver and transmitter can be interrupt controlled.
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SCI Port Interrupts 8.5.1 SCI Baud Rate Calculation The internally generated serial clock is determined by the device clock frequency (CLKOUT) and the baud rate select registers. The SCI uses the 16-bit value of the baud select registers to select one of the 64K different serial clock rates possible for a given device clock. See the bit descriptions in section 8.6.3, Baud-Select Registers, for the formula to use to calculate the SCI Asynchronous Baud. Table 8–3.
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SCI Module Registers 8.6 SCI Module Registers The functions of the SCI are software configurable. Sets of control bits, organized into dedicated bytes, are programmed to initialize the desired SCI communications format. This includes operating mode and protocol, baud value, character length, even/odd parity or no parity, number of stop bits, and interrupt priorities and enables. The SCI is controlled and accessed through registers listed in Figure 8–9, and described in the sections that follow.
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SCI Module Registers 8.6.1 SCI Communication Control Register The SCI communication control (SCICCR) register defines the character format, protocol, and communications mode used by the SCI. Figure 8–10.
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SCI Module Registers Bit 3 ADDR/IDLE MODE. SCI multiprocessor mode control bit. This bit selects one of the multiprocessor protocols 0 Idle-line mode protocol selected 1 Address-bit mode protocol selected Multiprocessor communication is different from the other communication modes because it uses SLEEP and TXWAKE functions (bits SCICTL1.2 and SCICTL1.3, respectively). The idle-line mode is usually used for normal communications because the address-bit mode adds an extra bit to the frame.
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SCI Module Registers 8.6.2 SCI Control Register 1 The SCI control register 1 controls the receiver/transmitter enable, TXWAKE and SLEEP functions, and the SCI software reset. Figure 8–11.SCI Control Register 1 (SCICTL1) — Address 7051h 7 6 5 4 3 2 1 0 Reserved RX ERR INT ENA SW RESET Reserved TXWAKE SLEEP TXENA RXENA R-0 RW-0 RW-0 R-0 RS-0 RW-0 RW-0 RW-0 Note: R = Read access, W = Write access, S = Set only, -0 = value after reset Bit 7 Reserved.
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SCI Module Registers Table 8–5. SW RESET-Affected Flags SCI Flag Register.Bit Value After SW RESET TXRDY SCICTL2.7 1 TX EMPTY SCICTL2.6 1 RXWAKE SCIRXST.1 0 PE SCIRXST.2 0 OE SCIRXST.3 0 FE SCIRXST.4 0 BRKDT SCIRXST.5 0 RXRDY SCIRXST.6 0 RX ERROR SCIRXST.7 0 Once SW RESET is asserted, the flags are frozen until the bit is de-asserted. Bit 4 Reserved. Reads return zero; writes have no effect. Bit 3 TXWAKE. SCI transmitter wakeup method select.
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SCI Module Registers tus bits (SCIRXST.5–2: BRKDT, FE, OE, and PE) unless the address byte is detected. This bit is not cleared when the address byte is detected. Bit 1 TXENA. SCI transmitter enable. Data is transmitted through the SCITXD pin only when TXENA is set. If reset, transmission is halted but only after all data previously written to SCITXBUF has been sent. Bit 0 0 Transmitter disabled 1 Transmitter enabled RXENA. SCI receiver enable.
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SCI Module Registers 8.6.3 Baud-Select Registers The values in the baud-select registers (SCIHBAUD and SCILBAUD) specify the baud rate for the SCI. Figure 8–12. Baud-Select MSbyte Register (SCIHBAUD) — Address 7052h 15 14 13 12 11 10 9 8 BAUD15 (MSB) BAUD14 BAUD13 BAUD12 BAUD11 BAUD10 BAUD9 BAUD8 RW-0 RW-0 RW-0 RW-0 RS-0 RW-0 RW-0 RW-0 Note: R = Read access, W = Write access, S = Set only, -0 = value after reset Figure 8–13.
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SCI Module Registers 8.6.4 SCI Control Register 2 SCI control register 2 enables the receive-ready, break-detect, and transmitready interrupts as well as transmitter-ready and -empty flags. Figure 8–14. SCI Control Register 2 (SCICTL2) — Address 7054h 7 6 5–2 1 0 TXRDY TX EMPTY Reserved RX/BK INT ENA TX INT ENA R-1 R-1 R-0 RW-0 RW-0 Note: R = Read access, W = Write access, -n = value after reset Bit 7 TXRDY. Transmitter buffer-register ready flag.
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SCI Module Registers 8.6.5 Receiver Status Register The receiver status (SCIRXST) register contains seven bits that are receiver status flags (two of which can generate interrupt requests). Each time a complete character is transferred to the receive buffers (SCIRXEMU and SCIRXBUF), the status flags are updated. Each time the buffers are read, the flags are cleared. Figure 8–16 on page 8-29 shows the relationships between several of the register’s bits. Figure 8–15.
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SCI Module Registers causes a receiver interrupt to be generated if the RX/BK INT ENA bit is a 1, but it does not cause the receiver buffer to be loaded. A BRKDT interrupt can occur, even if the receiver SLEEP bit is set to 1. BRKDT is cleared by an active SW RESET or by a system reset. It is not cleared by receipt of a character after the break is detected. In order to receive more characters, the SCI must be reset by toggling the SW RESET bit or by a system reset. Bit 4 0 No break condition.
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SCI Module Registers Bit 1 RXWAKE. Receiver wakeup-detect flag. A value of 1 in this bit indicates detection of a receiver wakeup condition. In the address bit multiprocessor mode (SCICCR.3 = 1), RXWAKE reflects the value of the address bit for the character contained in SCIRXBUF. In the idleline multiprocessor mode, RXWAKE is set if the SCIRXD data line is detected as idle.
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SCI Module Registers SCIRXEMU is not physically implemented, it is just a different address location to access the SCIRXBUF register without clearing the RXRDY flag. Figure 8–17. Emulation Data Buffer Register (SCIRXEMU) — Address 7056h 7 6 5 4 3 2 1 0 ERXDT7 ERXDT6 ERXDT5 ERXDT4 ERXDT3 ERXDT2 ERXDT1 ERXDT0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 Note: R = Read access, -0 = value after reset 8.6.6.
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SCI Module Registers 8.6.8 Priority Control Register The Priority Control Register contains the receiver and transmitter interrupt priority select bits and controls the SCT operation on the XDS emulator during program suspends such as hitting a breakpoint. Figure 8–20.
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Chapter 9 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) is a high-speed synchronous serial input/ output (I/O) port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communications between the DSP controller and external peripherals or another controller.
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Differences vs. ’C240 SPI 9.1 Differences vs. ’C240 SPI This SPI has 16-bit transmit and receive capability, with double-buffered transmit and double-buffered receive. All data registers are 16-bits wide. The SPI is no longer limited to a maximum transmission rate of CLKOUT / 8 in slave mode. The maximum transmission rate in both slave mode and master mode is now CLKOUT / 4.
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Differences vs. ’C240 SPI - State control logic - Memory-mapped control and status registers The basic function of the strobe (SPISTE) pin is to act as a transmit enable input for the SPI module in slave mode. It stops the shift register so it cannot receive data and puts the SPISOMI pin in the high-impedance state. Figure 9–1. SPI Module Block Diagram SPIRXBUF.15–0 Overrun INT ENA Receiver overrun SPIRXBUF buffer register SPI PRIORITY SPISTS.7 SPIPRI.6 SPICTL.4 SPITXBUF.
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SPI Control Registers 9.2 SPI Control Registers Nine registers inside the SPI module (listed in Table 9–1) control the SPI operations: - SPICCR (SPI configuration control register). Contains control bits used for SPI configuration J SPI module software reset J SPICLK polarity selection J Four SPI character-length control bits - SPICTL (SPI operation control register).
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SPI Control Registers Table 9–1.
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SPI Operation 9.3 SPI Operation This section describes the operation of the SPI. Included are explanations of the operation modes, interrupts, data format, clock sources, and initialization. Typical timing diagrams for data transfers are given. 9.3.1 Introduction to Operation Figure 9–2 shows typical connections of the SPI for communications between two controllers: a master and a slave. The master initiates data transfer by sending the SPICLK signal.
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SPI Operation Figure 9–2. SPI Master/Slave Connection SPI master (master/slave = 1) SPIRXBUF.15–0 Slave in/ SPISIMO master out SPI slave (master/slave = 0) SPISIMO Serial input buffer SPIRXBUF SPIRXBUF.15–0 Serial input buffer SPIRXBUF SPISTE SPI strobe SPIDAT.15–0 SPISOMI Shift register (SPIDAT) LSB MSB SPICLK SPISTE SPIDAT.15–0 Slave out/ master in Serial clock SPISOMI Shift register (SPIDAT) MSB SPICLK SPITXBUF.15–0 SPITXBUF.
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SPI Operation - If there is valid data in the transmit buffer SPITXBUF, as indicated by the TXBUF FULL bit in SPISTS, this data is transferred to SPIDAT and is transmitted; otherwise, SPICLK stops after all bits have been shifted out of SPIDAT. - If the SPI_INT_ENA bit (SPICTL.0) is set to 1, an interrupt is asserted. In a typical application, the SPISTE pin could serve as a chip enable pin for slave SPI devices.
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SPI Interrupts 9.4 SPI Interrupts Five control bits are used to initialize the SPI’s interrupts: - SPI_INT_ENA bit (SPICTL.0) - SPI_INT_FLAG bit (SPISTS.6) - OVERRUN_INT_ENA bit (SPICTL.4) - RECEIVER_OVERRUN flag bit (SPISTS.7) - SPI_PRIORITY bit (SPIPRI.6) 9.4.1 SPI_INT_ENA Bit (SPICTL.0) When the SPI interrupt enable bit is set and an interrupt condition occurs, the corresponding interrupt is asserted. 9.4.2 0 Disable SPI interrupts 1 Enable SPI interrupts SPI_INT_FLAG Bit (SPISTS.
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SPI Interrupts 9.4.3 OVERRUN_INT_ENA Bit (SPICTL.4) Setting the overrun interrupt enable bit allows the assertion of an interrupt whenever the RECEIVER_OVERRUN flag bit (SPISTS.7) is set by hardware. Interrupts generated by SPISTS.7 and by the SPI_INT_FLAG (SPISTS.6) bit share the same interrupt vector. 9.4.4 0 Disable RECEIVER_OVERRUN flag bit interrupts. 1 Enable RECEIVER_OVERRUN flag bit interrupts. RECEIVER_OVERRUN_FLAG Bit (SPISTS.
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SPI Interrupts Example 9–1. Transmission of Bit from SPIRXBUF Conditions: 1) Transmission character length = 1 bit (specified in bits SPICCR.3–0) 2) The current value of SPIDAT = 737Bh SPIDAT (before transmission) 0 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 SPIDAT (after transmission) (TXed) 0 ← 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 x ← (RXed) SPIRXBUF (after transmission) 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 Note: 9.4.7 x x = 1 if SPISOMI data is high; x = 0 if SPISOMI data is low; master mode is assumed.
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SPI Interrupts - For SPIBRR = 0, 1, or 2: SPI Baud Rate = CLKOUT 4 where: CLKOUT = CPU clock frequency of the device SPIBRR = Contents of the SPIBRR in the master SPI device To determine what value to load into SPIBRR, you must know the device system clock (CLKOUT) frequency (which is device-specific) and the baud rate at which you will be operating. Example 9–2 shows how to determine the maximum baud rate at which a ’C24x can communicate. Assume that CLKOUT = 30 MHz. Example 9–2.
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SPI Interrupts - Rising Edge With Delay. The SPI transmits data one half-cycle ahead of the rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. The selection procedure for the SPI clocking scheme is shown in Table 9–2. Examples of these four clocking schemes relative to transmitted and received data are shown in Figure 9–3. Table 9–2. SPI Clocking Scheme Selection Guide CLOCK POLARITY (SPICCR.6) CLOCK PHASE (SPICTL.
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SPI Interrupts For the SPI, the SPICLK symmetry is retained only when the result of (SPIBRR + 1) is an even value. When (SPIBRR + 1) is an odd value and SPIBRR is greater than 3, the SPICLK becomes asymmetrical. The low pulse of the SPICLK is one CLKOUT longer than the high pulse when the CLOCK_POLARITY bit is clear (0). When the CLOCK_POLARITY bit is set to 1, the high pulse of the SPICLK is one CLKOUT longer than the low pulse, as shown in Figure 9–4. Figure 9–4.
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SPI Interrupts 9.4.10 Proper SPI Initialization Using the SPI SW RESET Bit To prevent unwanted and unforeseen events from occurring during or as a result of initialization changes, clear the SPI SW RESET bit (SPICCR.7) before making initialization changes, and then set this bit after initialization is complete. Do not change SPI configuration when communication is in progress. 9.4.
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SPI Interrupts Figure 9–5. Five Bits per Character Master SPI Int flag Slave SPI Int flag A B C D E F G H I J SPISOMI from slave 7 6 5 4 3 7 6 5 4 3 7 6 5 4 3 7 6 5 4 3 SPISIMO from master SPICLK signal options: CLOCK POLARITY = 0 CLOCK PHASE = 0 CLOCK POLARITY = 0 CLOCK PHASE = 1 CLOCK POLARITY = 1 CLOCK PHASE = 0 CLOCK POLARITY = 1 CLOCK PHASE = 1 SPISTE A. B. C. D. E. F G. H. I. J. Slave writes 0D0h to SPIDAT and waits for the master to shift out the data.
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SPI Control Registers 9.5 SPI Control Registers The SPI is controlled and accessed through registers in the control register file. Figure 9–6 lists the SPI control registers and bit numbers. Figure 9–6. SPI Control Registers Bit number Addr Addr.
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SPI Control Registers 9.5.1 SPI Configuration Control Register (SPICCR) The SPI Configuration Control Register (SPICCR) controls the setup of the SPI for operation. Figure 9–7. SPI Configuration Control Register (SPICCR) — Address 7040h 7 6 5–4 3 2 1 0 SPI_SW_ RESET CLOCK_ POLARITY Reserved SPICHAR3 SPICHAR2 SPICHAR1 SPICHAR0 RW-0 RW-0 R-0 RW-0 RW-0 RW-0 RW-0 Note: R = Read access, W = Write access, -0 = value after reset Bit 7 Bit 6 SPI_SW_RESET. SPI Software Reset.
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SPI Control Registers 1 Data is output on falling edge and input on rising edge. When no SPI data is used, SPICLK is at high level. The data input and output edges depend on the value of the CLOCK_PHASE bit (SPICTL.3) as follows: - CLOCK_PHASE = 0: Data is output on the falling edge of the SPICLK signal; input data is latched on the rising edge of the SPICLK signal.
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SPI Control Registers 9.5.2 SPI Operation Control Register (SPICTL) The SPICTL operation control register controls data transmission, the SPI’s ability to generate interrupts, the SPICLK phase, and the operational mode (slave or master). Figure 9–8.
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SPI Control Registers impedance state. If this bit is disabled during a transmission, the transmit shift register continues to operate until the previous character is shifted out. When the TALK bit is disabled, the SPI is still able to receive characters and update the status flags. TALK is cleared (disabled) by a system reset. 0 Disables transmission: - Slave mode operation: If not previously configured as a general- purpose I/O pin, the SPISOMI pin will be put in the highimpedance state.
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SPI Control Registers one interrupt sequence each time this bit is set if the OVERRUN_INT_ENA bit (SPICTL.4) is set high. The bit is cleared in one of three ways: - Writing a 1 to this bit - Writing a 0 to SPI_SW_RESET (SPICCR.7) - Resetting the system If the OVERRUN_INT_ENA bit (SPICTL.4) is set, the SPI requests only one interrupt upon the first occurance of setting the RECEIVER_OVERRUN flag bit. Subsequent overruns will not request additional interrupts if this flag bit is already set.
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SPI Control Registers 9.5.4 SPI Baud Rate Register (SPIBRR) The SPIBRR contains the bits used for baud-rate selection. Figure 9–10. SPI Baud Rate Register (SPIBRR) — Address 7044h 7 6 5 4 3 2 1 0 Reserved SPI BIT RATE 6 SPI BIT RATE 5 SPI BIT RATE 4 SPI BIT RATE 3 SPI BIT RATE 2 SPI BIT RATE 1 SPI BIT RATE 0 R-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 Note: R = Read access, W = Write access, -0 = value after reset Bit 7 Reserved. Reads return zero; writes have no effect.
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SPI Control Registers 9.5.5 SPI Emulation Buffer Register (SPIRXEMU) The SPIRXEMU contains the received data. Reading the SPIRXEMU does not clear the SPI INT FLAG bit (SPISTS.6). This is not a real register but a dummy address from which the contents of SPIRXBUF can be read by the emulator without clearing the SPI_INT_FLAG. Figure 9–11.
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SPI Control Registers 9.5.6 SPI Serial Receive Buffer Register (SPIRXBUF) The SPIRXBUF contains the received data. Reading the SPIRXBUF clears the SPI_INT_FLAG bit (SPISTS.6). Figure 9–12.
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SPI Control Registers 9.5.7 SPI Serial Transmit Buffer Register (SPITXBUF) The SPITXBUF stores the next character to be transmitted. Writing to this register sets the TX_BUF_FULL (SPISTS.5) flag. When transmission of the current character is complete, the contents of this register are automatically loaded in SPIDAT and the TX_BUF_FULL flag is cleared. If no transmission is currently active, data written to this register falls through into the SPIDAT register and the TX_BUF_FULL flag is not set.
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SPI Control Registers 9.5.8 SPI Serial Data Register (SPIDAT) The SPIDAT is the transmit/receive shift register. Data written to the SPIDAT is shifted out (MSB) on subsequent SPICLK cycles. For every bit shifted out (MSB) of the SPI, a bit is shifted into the LSB end of the shift register. Figure 9–14.
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SPI Control Registers 9.5.9 SPI Priority Control Register (SPIPRI) The SPIPRI selects the interrupt priority level of the SPI interrupt and controls the SPI operation on the XDS emulator during program suspends, such as hitting a breakpoint. Figure 9–15. SPI Priority Control Register (SPIPRI) — Address 704Fh 7 6 Reserved SPI_ PRIORITY R-0 RW Note: 4 SPI_SUSP_ SPI_SUSP_ SOFT FREE RW RW-0 3–0 Reserved R-0 R = Read access, W = Write access, -0 = value after reset Bit 7 Reserved.
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SPI Example Waveforms 9.6 SPI Example Waveforms Figure 9–16. CLOCK_POLARITY = 0, CLOCK_PHASE = 0 (All data transitions are during the rising edge. Inactive level is low.
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SPI Example Waveforms Figure 9–17. CLOCK_POLARITY = 0, CLOCK_PHASE = 1 (Add data transitions are during the rising edge, but delayed by half clock cycle. Inactive level is low.
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SPI Example Waveforms Figure 9–18. CLOCK_POLARITY = 1, CLOCK_PHASE = 0 (All data transitions are during the falling edge. Inactive level is high.
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SPI Example Waveforms Figure 9–19. CLOCK_POLARITY = 1, CLOCK_PHASE = 1 (Add data transitions are during the falling edge, but delayed by half clock cycle. Inactive level is high.
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SPI Example Waveforms Figure 9–20. SPISTE Behavior in Master Mode (Master lowers SPISTE during the entire 16 bits of transmission.
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SPI Example Waveforms Figure 9–21. SPISTE Behavior in Slave Mode (Slave’s SPISTE is lowered during the entire 16 bits of transmission.
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Chapter 10 CAN Controller Module This chapter describes the controller area network (CAN) module available on some members of the ’24x/’240x family. The interface signals, configuration registers, and mailbox RAM are described in detail; however, the CAN protocol itself is not discussed in depth. For details on the protocol, refer to CAN Specifications, Version 2.0, by Robert Bosch GmBH, Germany.
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Introduction 10.1 Introduction The CAN peripheral supports the following features: - Full implementation of CAN protocol, version 2.
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Overview of the CAN Network 10.2 Overview of the CAN Network The controller area network (CAN) uses a serial multimaster communication protocol that efficiently supports distributed real-time control with a very high level of data integrity, and communication speeds of up to 1 Mbps. The CAN bus is ideal for applications operating in noisy and harsh environments, such as in the automotive and other industrial fields that require reliable communication.
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Overview of the CAN Network Figure 10–1. CAN Data Frame Bit length 1 12 or 32 Start bit 6 0–8 bytes 16 Control bits Data field CRC bits 7 End Acknowledge Arbitration field which contains: - 11-bit identifier + RTR bit for standard frame format - 29-bit identifier + SRR bit + IDE bit + RTR bit for extended frame format Where: RTR = Remote Transmission Request SRR = Substitute Remote Request IDE = Identifier Extension Note: 2 Unless otherwise noted, numbers are amount of bits in field. 10.2.
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Overview of the CAN Network The CAN module is a 16-bit peripheral that accesses the following: - Control/status registers - Mailbox RAM Control/Status Registers: The CPU performs 16-bit accesses to the control/ status registers. The CAN peripheral always presents full 16-bit data to the CPU bus during read cycles. Mailbox RAM: Writing/reading from the mailbox RAM is always wordwise (16 bits) and the RAM always presents the full 16-bit word on the bus.
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Overview of the CAN Network 10.2.3 Memory Map Figure 10–3 shows memory space, and Table 10–2 and Table 10–3 give the register and mailbox locations in the CAN module. Figure 10–3.
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Overview of the CAN Network Table 10–2.
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Overview of the CAN Network The mailboxes are located in one 48 × 16 RAM with 16-bit access and can be written to or read by the CPU (user) or CAN. The CAN write or read access, as well as the CPU read access, needs one clock cycle. The CPU write access needs two clock cycles because the CAN controller performs a read-modifywrite cycle; and therefore, inserts one wait state for the CPU. Table 10–3 shows the mailbox locations in the RAM. Table 10–3.
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Message Objects 10.3 Message Objects CAN allows messages to be sent, received, and stored by using data frames. Figure 10–4 illustrates the structure of the data frames with extended and standard identifiers. Figure 10–4. CAN Data Frame S O F Standard Identifier 11 bit S R R I D E Extended Identifier 18 bit S O F Standard Identifier 11 bit R T R r 1 r 0 DLC Data Byte 0 Data Byte 1 ... Data Byte 6 Data Byte 7 C R C A C K E O F R T R I D E r 0 DLC Data Byte 0 Data Byte 1 ...
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Message Objects - CRC: contains a 16-bit checksum calculated on most parts of the mes- sage. This checksum is used for error detection. - ACK: Data Acknowledge - EOF: End of Frame 10.3.1 Mailbox Layout 1) Mailbox RAM: The mailbox RAM is the area where the CAN frames are stored before they are transmitted, and after they are received. Each mailbox has four 16-bit registers which can store a maximum of 8 bytes (MBOXnA, MBOXnB, MBOXnC, and MBOXnD).
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Message Objects Bit 13 AAM. Auto Answer Mode Bit 0 Transmit The mailbox does not reply to remote requests mailbox automatically. If a matching identifier is received, it is not stored. Receive No influence on a receive mailbox. mailbox 1 Transmit If a matching remote request is received, the CAN mailbox Peripheral answers by sending the contents of the mailbox. Receive No influence on a receive mailbox. mailbox This bit is only used for mailboxes 2 and 3. Bits 12–0 IDH[28:16].
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Message Objects Bits 3–0 DLC. Data Length Code This value determines how many data bytes are used for transmission or reception. 0000 0 bytes 0010 2 bytes 0100 4 bytes 0110 6 bytes 1000 8 bytes 10.3.2 Message Buffers Message storage is implemented by RAM. The contents of the storage elements are used to perform the functions of acceptance filtering, transmission, and interrupt handling.
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Message Objects During accesses to the data field or control field, it is critical that the data does not change while the CAN module is reading it. Therefore, a write access to the data field or control field is disabled for a receive mailbox. For transmit mailboxes, the access is usually denied if the transmit request set (TRS) bit or the transmit request reset (TRR) bit is set. In these cases, a write-denied interrupt flag (WDIF) is asserted.
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Message Objects case, the stored message is overwritten with the new data if the overwrite protection control (OPC) bit is cleared. Otherwise, the next mailboxes are checked. Note: For the mailbox interrupt flag (MIFn) bits in the CAN_IFR register to be set, the corresponding bits in the CAN_IMR register must be enabled.
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Message Objects The CPU may then perform the access and clear the CDR to tell the CAN module that the access is finished. Until the CDR is cleared, the transmission of this mailbox is not performed. Since the TRS bit is not affected by the CDR, a pending transmission is stacked after the CDR is cleared. Thus, the newest data will be sent. In order to change the identifier in the mailbox, the message object must be disabled first (ME bit in the MDER = 0).
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Message Objects Figure 10–8.
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Message Objects reception, mailboxes 3 and 2 are checked before mailboxes 1 and 0. Figure 10–9 illustrates the LAMn_H high word and Figure 10–10 illustrates the LAMn_L low word. Figure 10–9. Local Acceptance Mask Register n (0, 1) High Word (LAMn_H) 15 14–13 12–0 LAMI Reserved LAMn[28:16] RW-0 Note: RW-0 R = Read access; W = Write access; value following dash (–) = value after reset Bit 15 LAMI. Local acceptance mask identifier extension bit.
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CAN Control Registers 10.4 CAN Control Registers The control register bits allow mailbox functions to be manipulated. Each register performs a specific function, such as enabling or disabling the mailbox, controlling the transmit/receive mail function, and handling interrupts. 10.4.1 Mailbox Direction/Enable Register (MDER) The Mailbox Direction/Enable register (MDER) consists of the Mailbox Enable (ME) and the Mailbox Direction (MD).
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CAN Control Registers Mailbox enable bits are defined as follows: 0 1 Disable mailbox Enable mailbox 10.4.2 Transmit Control Register (TCR) The transmit control register (TCR) contains bits that control the transmission of messages (see Figure 10–12). The control bits to set or reset a transmission request (TRS and TRR, respectively) can be written independently. In this way, a write access to these registers does not set bits that were reset because of a completed transmission.
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CAN Control Registers Bits AAn are reset by writing a 1 from the CPU. Writing a 0 has no effect. If the CPU tries to reset a bit and the CAN tries to set the bit at the same time, the bit is set. TRSn: Transmission Request Set (for mailbox n) If TRSn is set, write access to the corresponding mailbox is denied, and the message in mailbox n will be transmitted. Several TRS bits can be set simultaneously. TRS bits can be set by the CPU (user) or the CAN module and reset by internal logic.
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CAN Control Registers The status of the TRR bits can be read from the TRS bits. For example, if TRS is set and a transmission is ongoing, TRR can only be reset by the actions described above. If the TRS bit is reset and the TRR bit is set, no effect occurs because the TRR bit will be immediately reset. 10.4.3 Receive Control Register (RCR) The receive control register (RCR) contains the bits which control the reception of messages and remote frame handling. Figure 10–13.
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CAN Control Registers If one or more RML bits in the RCR register are set, the RMLIF in the IF register is also set. This may initiate an interrupt if the RMLIM bit in the IM register is set. RMPn: Receive Message Pending (for mailbox n) If a received message is stored in a mailbox n, the bit RMPn is set. The RMP bits can only be reset by the CPU and are set by the CAN internal logic. The bits RMPn and RMLn are cleared by writing a 1 to the RMPn bit at the corresponding bit location.
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CAN Control Registers Bits 15–14 Reserved Bit 13 SUSP. Action on emulator suspend. The value of SUSP bit has no effect on the receive mailboxes. Bit 12 Bit 11 0 Soft mode. The peripheral shuts down during suspend after the current transmission is completed. 1 Free mode. The peripheral continues to run in suspend. CCR. Change Configuration Request 0 The CPU requests normal operation. It also exits the bus-off state after the obligatory bus-off recovery sequence.
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CAN Control Registers Bit 8 CDR. Change Data Field Request The CDR bit is applicable for mailboxes 2 and 3 only and in the following situation: 1) either (or both) of these mailboxes are configured for transmission and 2) the corresponding AAM bit is set. Bit 7 Bit 6 0 The CPU requests normal operation. 1 The CPU requests write access to the data field of the mailbox in MBNR (located also in MCR). The CDR bit must be cleared by the CPU after accessing the mailbox.
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CAN Control Registers Figure 10–15. Bit Configuration Register 2 (BCR2) — Address 7104h 15–8 Reserved 7–0 BRP[7:0] RW-0 Note: R = Read access; W = Write access; value following dash (–) = value after reset Bits 15–8 Reserved. Bits 7–0 BRP. Baud Rate Prescaler Bits 7:0 of this field specify the duration of a time quantum (TQ) in CAN module system clock units. The length of one TQ is defined by: TQ = BRP+ 1 I CLK where ICLK is the frequency of the CAN module system clock,which is the same as CLKOUT.
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CAN Control Registers Bits 9–8 SJW. Synchronization jump width SJW indicates by how many units of TQ a bit is allowed to be lengthened or shortened when resynchronizing with the receive data stream on the CAN bus. The synchronization is performed either with the falling edge (SBG = 0) or with both edges (SBG = 1) of the bus signal. SJW is programmable from 1 to 4 TQ. Bit 7 SAM.
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CAN Control Registers CAN Bit Timing Figure 10–17. CAN Bit Timing Nominal bit time SYNCSEG SJW SJW TSEG1 TSEG2 Sample point Transmit point Baud rate is calculated as follows (in bits per second): Baud rate= I CLK (BRP + 1) × Bit Time where, Bit Time = number of TQ per bit Bit Time = (TSEG1 + 1) + (TSEG2 + 1) + 1 ICLK = CAN module system clock frequency (same as CLKOUT) BRP = Baud rate prescaler Table 10–4.
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Status Registers 10.5 Status Registers The two status registers are the global status register (GSR) and the error status register (ESR). As indicated by their names, GSR provides information for all functions of the CAN peripheral and ESR provides information about any type of error encountered. 10.5.1 Global Status Register (GSR) Figure 10–18.
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Status Registers Bit 2 Reserved. Bit 1 RM. The CAN module is in the Receive Mode. This bit reflects what the CBM is actually doing regardless of mailbox configuration. Bit 0 0 The CAN core module is not receiving a message. 1 The CAN core module is receiving a message. TM. The CAN module is in the Transmit Mode. This bit reflects what the CBM is actually doing regardless of mailbox configuration. 0 The CAN core module is not transmitting a message.
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Status Registers Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 10-30 BEF. Bit Error Flag 0 The CAN module was able to send and receive correctly. 1 The received bit does not match the transmitted bit outside of the arbitration field; or during transmission of the arbitration field, a dominant bit was sent but a recessive bit was received. SA1. Stuck at dominant Error 0 The CAN module detected a recessive bit.
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Status Registers 10.5.3 CAN Error Counter Register (CEC) The CAN module contains two error counters: the receive error counter (REC) and the transmit error counter (TEC). The values of both counters can be read from the CEC register via the CPU interface. Figure 10–20. CAN Error Counter Register (CEC) — Address 7108h 15–8 TEC[7:0] R-0 7–0 REC[7:0] R-0 Note: R = Read access; value following dash (–) = value after reset After exceeding the error passive limit (128), REC is not increased any further.
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Interrupt Logic 10.6 Interrupt Logic There are two interrupt requests from the CAN peripheral to the peripheral interrupt expansion (PIE) controller, the mailbox interrupt and the error interrupt. Both interrupts can assert either a high-priority request or a low-priority request to the CPU. The following events may initiate an interrupt: - Mailbox Interrupt J A message was transmitted or received successfully. This event asserts the Mailbox interrupt.
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Interrupt Logic 10.6.1 CAN Interrupt Flag Register (CAN_IFR) The interrupt flag bits are set if the corresponding interrupt condition occurs. The appropriate mailbox interrupt request is asserted only if the corresponding interrupt mask in CAN_IMR register is set. The peripheral interrupt request stays active until the interrupt flag is cleared by the CPU by writing a 1 to the appropriate bit. An interrupt acknowledge does not clear the interrupt flags.
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Interrupt Logic There is one interrupt mask bit for each mailbox. If a message is received, the corresponding bit RMPn in the RCR is set. If a message is sent, the corresponding bit TA in the TCR register is set. The setting of the RMPn bit or the TAn bit also sets the appropriate MIFx flag in the IF register if the corresponding interrupt mask bit is set. The MIFx flag generates an interrupt. The MIMx mask bits determine if an interrupt can be generated by a mailbox. Bit 7 Reserved. Bit 6 RMLIF.
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Interrupt Logic 10.6.2 CAN Interrupt Mask Register (CAN_IMR) The setup for the interrupt mask register (see Figure 10–22) is the same as for the interrupt flag register (CAN_IFR) with the addition of the interrupt priority selection bits MIL and EIL. If a mask bit is set, the corresponding interrupt request to the PIE controller is enabled. Figure 10–22.
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Configuration Mode 10.7 Configuration Mode The CAN module must be initialized before activation. This is only possible when the module is in the configuration mode, which is set by programming CCR with 1. The initialization can be performed only if the status bit CCE confirms the request by getting 1. Afterwards, the bit configuration registers can be written. The module is activated again by programming the control bit CCR with zero. After a hardware reset, the configuration mode is active. Figure 10–23.
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Power-Down Mode (PDM) 10.8 Power-Down Mode (PDM) If the peripheral clocks are to be shut off by the device low-power mode, the CAN peripheral’s own low-power mode must be requested before a device low-power mode is entered by executing the IDLE instruction. Before the CPU enters its IDLE mode prior to the device low-power mode that potentially shuts off all device clocks, it must first request a CAN peripheral power down by writing a 1 to the PDR bit in MCR.
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Suspend Mode 10.9 Suspend Mode The suspend mode can operate in either Free mode, where the CAN peripheral continues to operate regardless of the suspend signal being active, or Soft mode, where the CAN peripheral stops operation at the end of the current transmission. Suspend mode is entered when the CPU activates the SUSPEND signal. The SUSP bit in MCR determines which of the two suspend modes (Free or Soft) is entered. When the module enters the Soft suspend mode, the status bit SMA is set.
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Suspend Mode Table 10–5. CAN Notation Notation Signification Register Bit No.
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Suspend Mode Table 10–5. CAN Notation (Continued) 10-40 Notation Signification Register Bit No.
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Chapter 11 Watchdog (WD) Timer The watchdog (WD) timer peripheral monitors software and hardware operations, and implements system reset functions upon CPU disruption. If the software goes into an improper loop, or if the CPU becomes temporarily disrupted, the WD timer overflows to assert a system reset. Most conditions that temporarily disrupt chip operation and inhibit proper CPU function can be cleared and reset by the watchdog function.
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Watchdog Timer Features 11.
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Watchdog Timer Features Figure 11–1.Block Diagram of the WD Module 6-bit freerunning counter /64} /32} /16} WDCLK /8} /4} /2} CLR Name Register WD prescale select bits 000 001 010 WDCR.2–0 WDPS2–0 WDCR.6 WDDIS WDKEY.7–0 WDCNTR WDKEY Watchdog Counter Register Watchdog Reset Key Register WDCR Watchdog Control Register 011 100 101 110 111 WD FLAG WDCR.7 WDCNTR.
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Control Registers 11.2 Control Registers Three registers control the WD operations: - WD Counter Register (WDCNTR) — This register contains the value of the WD counter. - WD Key Register (WDKEY) — This register clears the WDCNTR when a 55h value followed by an AAh value is written to WDKEY.
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Control Registers 11.2.2 Operation of WD Timers The WD timer is an 8-bit resetable incrementing counter that is clocked by the output of the prescaler. The timer protects against system software failures and CPU disruption by providing a system reset when the WDKEY register is not serviced before a watchdog overflow. This reset returns the system to a known starting point. Software then clears the WDCNTR register by writing a correct data pattern to the WD key logic.
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Control Registers Table 11–1 shows a typical sequence written to WDKEY after power-up. Table 11–1. Typical WDKEY Register Power-Up Sequence Sequential Step Value Written Result to WDKEY 1 AAh No action. 2 AAh No action. 3 55h WDCNTR is enabled to be reset by the next AAh. 4 55h WDCNTR is enabled to be reset by the next AAh. 5 55h WDCNTR is enabled to be reset by the next AAh. 6 AAh WDCNTR is reset. 7 AAh No action. 8 55h WDCNTR is enabled to be reset by the next AAh.
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Control Registers 11.2.4.2 WD Check Bit Logic The WD check bits (WDCR.5–3, described in detail in section 11.3.3 on page 11-9) are continuously compared to a constant value (1012). If writes to the WD check bits do not match this value, a system reset is generated. This functions as a logic check, in case the software improperly writes to the WDCR, or if an external stimulus (such as voltage spikes, EMI, or other disruptive sources) corrupt the contents of the WDCR. Writing to bits WDCR.
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Watchdog Control Registers 11.3 Watchdog Control Registers The WD module control registers are shown in Table 11–2 and discussed in detail in the following subsections. Table 11–2.
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Watchdog Control Registers 11.3.2 WD Reset Key Register The WD reset key register clears the WDCNTR register when a 55h followed by an AAh is written to WDKEY. Any combination of AAh and 55h is allowed, but only a 55h followed by an AAh resets the counter. Any other value causes a system reset. Figure 11–3.
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Watchdog Control Registers Bit 4 Bit 3 Bits 2–0 WDCHK1. Watchdog Check Bit 1. This bit must be written as a 0 when you write to the WDCR register, or else a system reset is asserted. This bit is always read as 0. 0 Normal operation continues if all check bits are written correctly. 1 System reset is asserted. WDCHK0. Watchdog Check Bit 0. This bit must be written as a 1 when you write to the WDCR register, or else a system reset is asserted. This bit is always read as 0. 0 System reset is asserted.
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Chapter 12 ’240x–’240 Family Compatibility This chapter describes the compatibility issues between the ’240x and ’240 family of processors. The software changes required between ’240 code and ’240x code have been kept to a minimum. A majority of the register addresses, bit positions, and functions are identical between the ’240 and ’240x devices. Topic Page 12.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2 Event Manager . . .
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General 12.1 General Low-power mode 2 (HALT) is the lowest power mode on the ’240x. It is similar to the LPM3 (oscillator power down) on the ’240. There is no equivalent to LPM2 (PLL power down) on the ’240. The low-power-mode bits are in a different register (SCSR1) and in different bit positions on the ’240x. Software reset is not available.
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Event Manager 12.2 Event Manager In order to port code from ’240 to ’240x: - The GP timer 3 must not be used. - The single-up count and single-up/down count modes of the GP timers must not be used. The decoding of the timer modes from the TMODE1–0 bits has changed, and this code will have to be modified when porting code from the ’240 to the ’240x. - The 32-bit timer mode cannot be used. - Capture 3 on the ’240 cannot be used, when porting code from the ’240 to the ’240x.
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Analog-to-Digital Analog-to-Digital Converter Converter / Serial Communications Interface / Serial Peripheral Interface / Watchdog Timer 12.3 Analog-to-Digital Converter When compared to the ’240 ADC, the ’240x ADC has been significantly enhanced. As a result, code written for the ’240 ADC cannot be ported to the ’240x. 12.4 Serial Communications Interface Some code changes are required.
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Chapter 13 ’24x–’240x Family Compatibility Topic Page 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2 ’24x–’240x DSP Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.4 Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Introduction 13.1 Introduction This chapter highlights the major differences (in terms of features/peripherals) between the ’240x and the ’24x (TMS320F243/’F241/’C242) family of DSP devices. The ’240x devices share most of the ’24x features; however, ’240x devices have some enhancements. The common features, differences, and enhancements are described in Table 13–1 and Table 13–2. Table 13–1.
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Introduction Table 13–2.
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’24x–’240x DSP Overview 13.2 ’24x–’240x DSP Overview Table 13–3. Features of ’24x and ’240x DSPs Device Feature ’LF2407 ’LF2406 ’LF2402 ’24x (’F243) Yes Yes Yes Yes DARAM 544 words 544 words 544 words 544 words SARAM – Program/Data 2K words 2K words – – Power Supply 3.3V Core 3.3V I/O 3.3V Core 3.3V I/O 3.3V Core 3.
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Memory Map 13.3 Memory Map 13.3.1 Program Space Figure 13–1.
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Memory Map 13.3.2 Data Space Figure 13–2.
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Memory Map 13.3.3 I/O Space The ’LF2407 is the only device which has all the I/O space enabled and is available through the external memory interface. All ’240x devices have two addresses in the I/O space as internal registers for Flash and wait-state generator. Table 13–4 explains the internal register addresses that are used. The external I/O space is reserved for all ’240x devices except the ’LF2407. Table 13–4.
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Flash Program Memory 13.4 Flash Program Memory The Flash module is generally used to provide permanent program storage. The Flash can emulate standard EEPROM or can be programmed and electrically erased many times to allow code development. The ’240x Flash is similar to that on the ’24x devices, with some key differences and enhancements. ’240x Flash features are as follows: - Flash run-time execution at 3.
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Flash Program Memory Table 13–5. Instructions for Entering and Exiting Flash Control Register Mode Mode ’C2xx Instruction Flash Array Access Mode IN Control Register Access Mode Note: OUT Description Dummy, 0FF0Fh Sets the Flash into normal run or operating mode (i.e., Flash read) (Note: Flash Control Registers are disabled in this mode.) Dummy, 0FF0Fh Sets the Flash into control mode, ready for Erase and Programming operations (i.e.
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Flash Program Memory Table 13–6. Flash Control Registers in Flash Control Mode Name Program Address Description PMPC XXX0h Pump Control Register. This register controls the charge pump. It contains the EXECUTE bit, two KEY bits that offer protection against inadvertent programming or erasing, and the PWRD bit that is used as an alternative to the POWERDOWN input signal. CTRL XXX1h Flash Control Register.
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Flash Program Memory Bits 15–4 Reserved Bit 3 PWR DWN. Power down bit Writing a 1 to this bit puts the Flash pumps into a very low current consumption mode. This register bit is mostly intended for test purposes; however, this bit can be used in normal operating mode also, if needed. Powerdown mode is entered if the PWRD bit is set high. Bit 2 KEY1. Execute key bit 1 This bit must be written as a 1 in the same access as the EXEC bit is set for the EXECUTE operation to start.
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Flash Program Memory Bits 15–10 Reserved Bit 9 WSVER En. Verification wait-state enable When active high, this bit enables the automatic generation of a wait state on all verification reads (ERASEVER, PROGVER, CMPCTVER, RDMRGN1, RDMRGN0) by pulling OREADY low for one cycle. When inactive low, verification reads will have zero wait states. Bit 8 PRECND Mode1 Bit 7 PRECND Mode0 Bit 6 ENG/R Mode2 Bit 5 ENG/R Mode1 Bit 4 ENG/R Mode0 Bits 3–0 FCM3–FCM0.
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Flash Program Memory 0101 CMPCT (Compaction mode). Set up charge pump and Flash core for compaction operation. Set this mode to start a compaction operation that pulls over-erased bits out of depletion. The CMPCT mode must be set prior to the access that sets the PMPC EXECUTE bit, by the delay defined in the Flash module specification. 0110 CMPCTVER (Compaction verify mode). This is used to test for bits erased into depletion. This sets up the charge pump and Flash core for the depletion test.
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Flash Program Memory Bits 15–3 Reserved Bit 2 TCR Enable. Test Control Register Enable This bit enables the Test Control Register (TCR) to the specific core corresponding to this ENAB register. This controls the TEZ input to the Flash core. This bit is only accessible if the TEST input is high. Bit 1 Standby. Standby mode Enable This bit, when active high, puts the Flash core into standby mode.
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Flash Program Memory Bits 15–4 Reserved Bits 3–0 Sect 4 Enable – Sect 1 Enable. Sector Enable Each Sector enable bit is used to protect or enable write and erase operations for each of the defined sectors in the Flash array.
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System Features 13.5 System Features This section presents some the system features that are new to the ’240x devices. Understanding these key features may help system initialization and ’24x-to-’240x migration. 13.5.1 Oscillator and PLL Unlike the ’24x device, the ’240x devices have a 5-pin PLL with a 3-bit ratio control to provide eight different CPU clock options.
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System Features 13.5.2 Watchdog Clock Watchdog clock generation logic is different in ’240x devices with respect to ’24x devices. Unlike the fixed PLL (x4) in ’24x, the ’240x devices have a variable clock from the PLL. This changes the input clock options for the watchdogmodule. The clock flow diagram below explains the watchdog clock generation logic. ’240x devices have a watchdog override bit in the SCSR2 register, which is similar to the WDDIS pin available on the ’24x devices.
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System Features 13.5.3 System Control Registers ’240x devices have two system control and status registers: SCSR1 and SCSR2 (see section 2.2.1 on page 2-3). These registers have control and status bits for several on-chip modules. These register bits should be initialized after reset to enable/disable on-chip functionality for the selected application. ’24x has only one SCSR register and all its on-chip peripherals are powered up after reset.
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System Features 13.5.3.2 Fast RD Strobe Operation ’LF2407 is the only device that supports external memory interface (XMIF) to expand the internal memory space with the addition of external memory devices. The interface offers decode signals for Program, Data, and I/O space. ’LF2407 external memory interface signals have critical timings while interfacing zero-wait-state memory at higher CPU clock speeds.
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Digital I/O (GPIO Pins) 13.6 Digital I/O (GPIO Pins) Some members of the ’240x family have more GPIO pins than the ’24x devices. This necessitates additional registers. The bit definitions for some multiplexed pins such as XF, CLKOUT, etc. are different from those of the ’24x. See Chapter 5 for more details. Note that when multiplexed I/O pins are in input mode, the pin is connected to both the I/O data register and the shared peripheral.
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Digital I/O (GPIO Pins) Table 13–10. ’LF2407 Shared Pin Configuration Shared Pin Functions Mux Control Bit # MCRx.
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Digital I/O (GPIO Pins) Table 13–10. ’LF2407 Shared Pin Configuration (Continued) Shared Pin Functions Mux Control Bit # MCRx.
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Event Manager Module (EVB) 13.7 Event Manager Module (EVB) The event manager module available on ’240x devices is identical to the event manager in the ’24x family. EVA and EVB are exactly identical modules, except that their registers start at 7400h and 7500h, respectively, in the peripheral space. The functional description of the event manager, available in the TMS320F243/F241/C242 DSP Controllers Reference Guide (literature number SPRU276C), is applicable to EVB as well.
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Appendix AppendixAA Programmable Register Address Summary Table A–1 shows the peripheral register map for ’240x devices. The shaded table entries represent the registers that are in addition to the ’24x registers. These details are also explained in the TMS320LF2407, TMS320LF2406, TMS320LF2402, TMS320LC2406, TMS320LC2404, TMS320LC2402 DSP Controllers Data Sheet (literature number SPRS094).
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Summary of Programmable Registers on the ’240x Table A–1.
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Summary of Programmable Registers on the ’240x Table A–1.
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Summary of Programmable Registers on the ’240x Table A–1.
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Summary of Programmable Registers on the ’240x Table A–1.
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Summary of Programmable Registers on the ’240x Table A–1.
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Summary of Programmable Registers on the ’240x Table A–1.
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Summary of Programmable Registers on the ’240x Table A–1.
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Appendix AppendixBA Program Examples This appendix provides: - A brief introduction to the tools used for generating executable COFF files that run on the ’240x devices. - Sample programs to test some of the peripherals available in the ’240x devices. This appendix is not intended to teach you how to use the software development tools.
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About About These These Program Program Examples B.1 About These Program Examples Figure B–1 illustrates the basic process for generating executable COFF files: 1) Use any ASCII editor to create: - An assembly language program (test.asm in the figure) - A linker command file (240x.cmd in the figure) that defines address ranges according to the architecture of the particular device and where the various sections of the user code should be located 2) Assemble the program.
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About These Program Examples Table B–1. Common Files For All Example Programs Program Functional Description 240x_PM.cmd Linker command file that defines the program, data, and I/O memory maps of the target hardware. It also locates the various sections in the user code into predetermined segments of memory. This .cmd file locates user code (vectors and .text sections) in program memory beginning at 0000h. 240x.h Header file that designates labels for the addresses of the various registers. vector.
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Program Examples B.2 Program Examples /******************************************************************************/ /* File Name: 240x_PM.cmd */ /* Description: Linker command file to place user code (vectors & .text) */ /* sections beginning at 0000h of program memory. .text is loaded at 40h. */ /* This file should be modified if it is desired to load code in B0 memory or */ /* if on–chip SARAM is to be used.
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Program Examples ;************************************************************************ ; File name: 240x.h ; ; Description: 240x register definitions, Bit codes for BIT instruction ;************************************************************************ ; 240x CPU core registers IMR IFR .set 0004h .set 0006h ; Interrupt Mask Register ; Interrupt Flag Register ; System configuration and interrupt registers SCSR1 SCSR2 DINR PIVR PIRQR0 PIRQR1 PIRQR2 PIACKR0 PIACKR1 PIACKR2 .set .set .set .set .set .
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Program Examples CHSELSEQ4 AUTO_SEQ_SR RESULT0 RESULT1 RESULT2 RESULT3 RESULT4 RESULT5 RESULT6 RESULT7 RESULT8 RESULT9 RESULT10 RESULT11 RESULT12 RESULT13 RESULT14 RESULT15 CALIBRATION .set .set .set .set .set .set .set .set .set .set .set .set .set .set .set .set .set .set .
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Program Examples T2PR T2CON .set 7407h .set 7408h ; GP Timer 2 period register ; GP Timer 2 control register COMCONA ACTRA DBTCONA .set 7411h .set 7413h .set 7415h ; Compare control register A ; Full compare Action control register A ; Dead–band timer control register A CMPR1 CMPR2 CMPR3 .set 7417h .set 7418h .set 7419h ; Full compare unit compare register1 ; Full compare unit compare register2 ; Full compare unit compare register3 CAPCONA CAPFIFOA .set 7420h .
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Program Examples CAP6FIFO .set 7525h ; Capture Channel 6 FIFO Top CAP4FBOT CAP5FBOT CAP6FBOT .set 7527h .set 7527h .set 7527h ; Bottom reg. of capture FIFO stack 4 ; Bottom reg. of capture FIFO stack 5 ; Bottom reg. of capture FIFO stack 6 EVBIMRA EVBIMRB EVBIMRC .set 752Ch .set 752Dh .set 752Eh ; Group A Interrupt Mask Register ; Group B Interrupt Mask Register ; Group C Interrupt Mask Register EVBIFRA EVBIFRB EVBIFRC .set 752Fh .set 7530h .
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Program Examples CANMSGID3L CANMSGID3H CANMSGCTRL3 CANMBX3A CANMBX3B CANMBX3C CANMBX3D .set .set .set .set .set .set .set 7218h 7219h 721Ah 721Ch 721Dh 721Eh 721Fh ; ; ; ; ; ; ; CAN CAN CAN CAN CAN CAN CAN Message ID for mailbox 3 (lower 16 bits) Message ID for mailbox 3 (upper 16 bits) RTR and DLC 2 of 8 bytes of Mailbox 3 2 of 8 bytes of Mailbox 3 2 of 8 bytes of Mailbox 3 2 of 8 bytes of Mailbox 3 CANMSGID4L CANMSGID4H CANMSGCTRL4 CANMBX4A CANMBX4B CANMBX4C CANMBX4D .set .set .set .set .set .
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Program Examples ;************************************************************ ; File name: vector.h ; Interrupt Vector declarations ; This section contains the vectors for various interrupts in ; the ’240x. Unused interrupts are shown to branch ; to a ”phantom” interrupt service routine which disables the ; watchdog and loops on itself. Users should replace the label ; PHANTOM with the label of their interrupt subroutines in case ; these interrupts are used.
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Program Examples ;================================================================================= * File Name: SPI.asm * Description: PROGRAM TO OUTPUT SERIAL DATA THROUGH THE SPI PORT * This program outputs a set of incrementing words (that roll over) through * the SPI. If a Digital–to–analog (DAC) converter is connected to the SPI, * the DAC outputs a sawtooth waveform. The program sends data to the serial DAC * by means of the SPI. For this example, the TLC5618 serial DAC from TI was used.
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Program Examples ;=========================================================================== ; SPI Initialization ;=========================================================================== SPI_INIT: LDP SPLK SPLK #SPICCR>>7 #000Fh, SPICCR #0006h, SPICTL SPLK #0002h, SPIBRR ;16 char bits, ;Enable master mode, normal clock ;and enable talk. ;Set up the SPI to max speed.
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Program Examples ;=========================================================================== * File Name: SCI.asm * Description: PROGRAM TO PERFORM A LOOPBACK IN THE SCI MODULE IN ’240x * An 8 bit value is transmitted through the SCITXD pin at a baud rate of * 9600 bits/sec. SCITXD–SCIRXD pins are connected together, if external * loopback is desired i.e. if it is desired to echo the bit–stream back. The SCI * receives the bit–stream and stores the received data in memory for verification.
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Program Examples ;=========================================================================== ;SCI TRANSMISSION TEST – starts here ;=========================================================================== SCI: XMIT_CHAR: LDP SPLK #0E1h #0FFFFh,MCRA LAR LAR LAR LAR LDP SPLK AR0, #SCITXBUF AR1, #SCIRXBUF AR2, #20h AR3, #60h #SCICCR>>7 #17h, SCICCR SPLK #0003h, SCICTL1 SPLK #0000h, SCICTL2 ;17 for internal ;loopback 07–External ;1 stop bit,odd parity,8 char bits, ;async mode, idle–line protocol ;
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Program Examples ;============================================================================* * File name : ADC.asm * * Description : PROGRAM TO INITIALIZE THE ADC MODULE OF 240x * * This program initializes the ADC module of the ’240x and does a conversion * * of all the analog input channels. The results of the conversion are * * available in the RESULTSn register, which can be accessed by the user * * application.
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Program Examples * Setup a maximum of 16 conversions SPLK #15, MAXCONV ; Setup for 16 conversions * Program the conversion sequence. This is the sequence of channels that will * be used for the 16 conversions.
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Program Examples ;========================================================================= * File name : GPIO_OUT.asm * Description : PROGRAM TO CHECK THE GPIO PINS OF 240x as outputs * * This program writes a running pattern of 0’s to the GPIO pins of 240x * * It ouputs a total of 8 bit patterns to the five GPIO ports (A,B,C,E,F) * * Each bit pattern forces a particular bit low and forces the other 7 * * bits high. This goes on in an endless loop.
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Program Examples MAIN LOOP DELAY D_LOOP PHANTOM B-18 SPLK SPLK SPLK SPLK #0FFFFh, #0FFFFh, #0FFFFh, #0FFFFh, PBDATDIR PCDATDIR PEDATDIR PFDATDIR LDP LAR #0 AR0,#300h LAR AR1,#7 MAR LACC LDP SACL SACL SACL SACL SACL *,AR0 *+,AR2 #00E1h PADATDIR PBDATDIR PCDATDIR PEDATDIR PFDATDIR CALL DELAY MAR BANZ B *,AR1 LOOP MAIN LAR RPT NOP BANZ RET AR2,#0FFFFh #0FFh ; and forced high ; ; ; ; AR0 points to bit pattern in ; data memory ; AR1 is the counter ; Load bit pattern in accumulator ; Output
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Program Examples ;========================================================================= * File name : GPIO_IN.asm * * Description : PROGRAM TO CHECK GPIO PINS OF 240x as inputs * * All GPIO bits are programmed as inputs and the values read from the * * GPIO pins are written in 60h,61h,62h,63h,64h of Data memory * ;========================================================================= .title ” 240x GPIO” .bss GPR0,1 ; Gen purp reg .include 240x.
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Program Examples LACL SACL LACL SACL LACL SACL LACL SACL B PHANTOM B-20 PBDATDIR *+ PCDATDIR *+ PEDATDIR *+ PFDATDIR *+ MAIN KICK_DOG B PHANTOM ;Resets WD counter
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Program Examples ;=============================================================================== * File name : REM_ANS.asm * * Description : PROGRAM TO INITIATE AUTO–ANSWER TO A REMOTE FRAME * * REQUEST IN CAN * * The two CAN modules must be connected to each other with appropriate * * termination resistors. Reception and transmission by MBX2. Low priority * * interrupt used. Transmit acknowledge for MBX2 is set after running this * * program and the message is transmitted.To be used along with REM_REQ.
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Program Examples ;************************************************************************** ; Enable 1 core interrupt ;************************************************************************** LDPK SPLK #0 #0000000000010000b, IMR ; core interrupt mask register |||||||||||||||| FEDCBA9876543210 SPLK CLRC #000ffh,IFR INTM ; ; ; Clear all core interrupt flags ; enable interrupt ;************************************************************************** ;******************** CAN Initialization*********
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Program Examples ;************************************************************************** LDP #DP_CAN2 SPLK #1111111111111111b,CANMSGID2H |||||||||||||||| FEDCBA9876543210 ; ; ; ; ; ; bit bit bit bit 0–12 13 14 15 upper 13 bits of extended identifier Auto answer mode bit Acceptance mask enable bit Identifier extension bit ; ; SPLK #1111111111111111b,CANMSGID2L |||||||||||||||| FEDCBA9876543210 ; bit 0–15 lower part of extended identifier ; ; SPLK #0000000000001000b,CANMSGCTRL2 |||||||||||
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Program Examples ; bit 12 W_CCE Change configuration request BIT BCND CANGSR,#0Bh W_CCE,NTC SPLK ; ; #0000000000000000b,CANBCR2 |||||||||||||||| FEDCBA9876543210 ; bit 0–7 ; bit 8–15 Baud rate prescaler Reserved SPLK ; ; ; ; ; ; ; ; bit bit bit bit bit bit 0–2 3–6 7 8–A B C–F ; Wait for Change config Enable #0000010101010111b,CANBCR1 |||||||||||||||| FEDCBA9876543210 TSEG1 TSEG2 Sample point setting (1: 3 times, 0: once) Synchronization jump width Synchronization on falling edge Reserved SPLK ;
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Program Examples GISR1: GISR2: GISR3: GISR4: GISR6: PHANTOM ; ; ; ; RET RET RET RET RET RET .end When data in MBX2 is transmitted in response to a ”Remote frame request,” the MBX2 data is copied from 300h onwards in DM. Note that TRS bit is not set for MBX2. The transmission of MBX2 data is automatic ,in response to a ”Remote frame request.
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Program Examples ;============================================================================== * File name : REM_REQ.asm * * Description : PROGRAM TO TRANSMIT A REMOTE FRAME REQUEST IN THE CAN OF 240x * * The two CAN modules must be connected to each other with appropriate * * termination resistors. Transmission of a remote frame by MBX3 and reception * * of the data frame in MBX0. To be used along with REM_ANS.
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Program Examples ;************************************************************************** ;******************** CAN Initialization*********************************** ;************************************************************************** LDP SPLK SPLK #DP_CAN #1001111111111111b,CANLAM0H #1111111111111111b,CANLAM0L ; Set LAM0 ; 1:don’t care SPLK #1011111111111111b,CANIMR ; Enable all interrupts ;************************************************************************** ;*********** Configure CA
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Program Examples ; bit 4 1: Remote frame SPLK ; ; ; ; ; ; bit bit bit bit 0–12 13 14 15 #1111111111111111b,CANMSGID0H |||||||||||||||| FEDCBA9876543210 upper 13 bits of extended identifier Auto answer mode bit Acceptance mask enable bit Identifier extension bit ; ; SPLK #1111111111111110b,CANMSGID0L |||||||||||||||| FEDCBA9876543210 ; bit 0–15 lower part of extended identifier SPLK ; ; #0000000000001000b,CANMSGCTRL0 |||||||||||||||| FEDCBA9876543210 ;*******************************************
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Program Examples ; bit 8–15 Reserved SPLK ; ; ; ; ; ; ; ; bit bit bit bit bit bit 0–2 3–6 7 8–A B C–F #0000010101010111b,CANBCR1 |||||||||||||||| FEDCBA9876543210 TSEG1 TSEG2 Sample point setting (1: 3 times, 0: once) Synchronization jump width Synchronization on falling edge Reserved ; ; SPLK #0000000000000000b,CANMCR |||||||||||||||| FEDCBA9876543210 ; bit 12 Change conf register W_NCCE BIT BCND CANGSR,#0Bh W_NCCE,TC ; Wait for Change config disable ;***************************************
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Program Examples BCND LOOP,NEQ PASS LDP SPLK #7h #0A000h,020h LOOP B LOOP GISR1: GISR2: GISR3: GISR4: GISR5: GISR6: PHANTOM B-30 RET RET RET RET RET RET RET .
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Program Examples ;========================================================================= * File name : EV_T1INT.asm * * Description : PROGRAM TO CHECK THE OPERATION OF TIMER1 IN EVA * * Mode: Continous Up/Down counting, x/128 * * Output: OF,UF,CMPR & PERIOD interrupts that toggles IOPB0,1,2,3 * ;========================================================================= .title ” EV test routine” ; Title .include ”240x.h” ; Variable and register declaration .include vector.
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Program Examples wait: GISR2: SPLK #0000011110000000b,EVAIFRA ; clear interrupts LDP SPLK CLRC #0 #0000000000000010b,IMR INTM NOP NOP B NOP LDP LACL XOR BCND LACL XOR BCND LACL XOR BCND LACL XOR BCND RET ; Enable INT2 ; main loop wait #PIVR >> 7h PIVR #002ah SISR2a,eq PIVR #0029h SISR29,eq PIVR #0028h SISR28,eq PIVR #0027h SISR27,eq ; ; ; ; Int2 GISR Peripheral page PIVR value T1 overflow ; T1 underflow ; T1 Compare ; T1 Period SISR2a: LDP SPLK CALL LDP LACC SACL CLRC RET #0E1h #0FF01h,PBDA
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Program Examples RET SISR27: DELAY D_LOOP LDP SPLK CALL LDP LACC SACL CLRC RET #0E1h #0FF08h,PBDATDIR DELAY #GPTCONA >> 7h #0080h EVAIFRA INTM LAR RPT NOP BANZ RET AR0,#01h #01h GISR1: GISR3: GISR4: GISR5: GISR6: RET RET RET RET RET PHANTOM RET ; Peripheral page ; Set IOPB3 ; ; ; ; Peripheral page clear period int. flag in EVAIFRA Enable all interrupts ; Gen. purpose delay ; Delay parameters may need to be ; modified for easy observation D_LOOP .
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Program Examples ;=========================================================================== * File name : CAP.asm * * Description : PROGRAM TO CHECK THE CAPTURE UNITS OF ’240X * * This program checks the Capture units of EVA & EVB. On each EV module, * * the capture units are setup to detect different transitions. On EVA, * * CAP1 detects a rising edge, CAP2 detects a falling edge and CAP3 detects * * both edges. All capture interrupts are enabled.
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Program Examples LDP SPLK SPLK SPLK #EVBIMRA>>7 #0FFFFh,EVBIFRA #0FFFFh,EVBIFRB #0FFFFh,EVBIFRC ; Peripheral page ; clear all EVB interrupt flags LAR MAR LDP SPLK SPLK AR7,#del ; Load AR7 with delay value *,AR7 ; Set ARP to ar7 #0E1h ; Peripheral page #1111111111111111b,MCRA ; enable all EV signals #1111111111111111b,MCRC ; enable all EV signals *===================================================================== * EVA Capture test * This portion of the code tests the EVA Capture unit.
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Program Examples * Load Capture registers SPLK SPLK #0011001001101100b,CAPCONA ; 0 clear capture registers ; 01–enable Capture 1,2 disable QEP ; 1 –enable Capture 3 ; 0 –reserved ; 0 –Use GPTimer 2 for CAP3 ; 1 –Use GPTimer 1 for CAP1,2 ; 0 –No ADC start on CAP3 interrupt ; 01 –CAP1 is rising edge detect ; 10 –CAP2 is falling edge detect ; 11 –CAP3 on both edges ; 00 –reserved #0000000000000111b,EVAIMRC ; 0000 0000 0000 0 ; 111, enable CAP3,CAP2,CAP1 ; interrupts LDP #6h ; ; ; ; Write the failure cod
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Program Examples SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK ; 10 – T2 CMP active hi ; 01 – T1 CMP active lo #0000000000000000b,T3CNT ; zero timer 3 count #0000000000000000b,T4CNT ; zero timer 4 count #0001011101000010b,T3CON ; 000 10 Cont, Up ; 111 x/128, ; 0 reserved for T3,Tenable select ; 1 Tenable for Timer 3 ; 00 Internal clk ; 00 cntr =0 ; 1 enable compare ; 0 use own period register #0001011111000011b,T4CON ; TSWT3=1: Use Timer 3 tenable bit ; SELT3PR=1: Use Timer 3 period ; register #111111111
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Program Examples ;===================================================================== ; Exit routine ;===================================================================== LDP #0h SPLK #0h,IMR ; Mask all interrupts LACC IFR ; Read Interrupt flags SACL IFR ; Clear all interrupt flags SETC INTM LDP #EVAIMRA>>7 ; Peripheral page SPLK #0h,EVAIMRA ; Mask all EVA interrupts SPLK #0h,EVAIMRB SPLK #0h,EVAIMRC SPLK #0FFFFh,EVAIFRA ; clear all EVA interrupt flags SPLK #0FFFFh,EVAIFRB SPLK #0FFFFh,EVAIFRC LDP #EVBI
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Program Examples XOR BCND RET #0038h SISR38,eq LDP SPLK LDP BLDD BLDD LACL XOR BCND LACL XOR BCND #GPTCONA >> 7h #0001h,EVAIFRC #0h #CAP1FIFO,70h #CAP1FIFO,71h 70h #0h CAP1FAIL,NEQ 71h #0h CAP1PASS,EQ LDP SPLK B #6h #5101h,51h END_INT LDP SPLK CLRC RET #6h #5100h,51h INTM LDP SPLK LDP BLDD BLDD LACL XOR BCND LACL XOR BCND #GPTCONA >> 7h #0002h,EVAIFRC #0h #CAP2FIFO,72h #CAP2FIFO,73h 72h #3F00h CAP2FAIL,NEQ 73h #3F00h CAP2PASS,EQ LDP SPLK B #6h #5201h,52h END_INT LDP SPLK CLRC RET #6h #5200h,52
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Program Examples LACL XOR BCND LACL XOR BCND 74h #0h CAP3FAIL,NEQ 75h #3F00h CAP3PASS,EQ LDP SPLK B #6h #5301h,53h END_INT LDP SPLK CLRC RET #6h #5300h,53h INTM LDP SPLK LDP BLDD BLDD LACL XOR BCND LACL XOR BCND #GPTCONB >> 7h #0001h,EVBIFRC #0h #CAP4FIFO,76h #CAP4FIFO,77h 76h #0h CAP4FAIL,NEQ 77h #0h CAP4PASS,EQ LDP SPLK B #6h #6101h,61h END_INT LDP SPLK CLRC RET #6h #6100h,61h INTM LDP SPLK LDP BLDD BLDD LACL XOR BCND LACL XOR BCND #GPTCONB >> 7h #0002h,EVBIFRC #0h #CAP5FIFO,78h #CAP5FIFO,79
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Program Examples CAP5PASS LDP SPLK CLRC RET #6h #6200h,62h INTM LDP SPLK LDP BLDD BLDD LACL XOR BCND LACL XOR BCND #GPTCONB >> 7h #0004h,EVBIFRC #0h #CAP6FIFO,7Ah #CAP6FIFO,7Bh 7Ah #0h CAP6FAIL,NEQ 7Bh #3F00h CAP6PASS,EQ LDP SPLK B #6h #6301h,63h END_INT LDP SPLK CLRC RET #6h #6300h,63h INTM SISR38: CAP6FAIL ; CAP6 SISR ; Peripheral page ; clear Capture flag ; Check FIFO values ; Report CAP6 error CAP6PASS ;====================================================================== ; Delay routine
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Appendix AppendixCA TMS320F240x Boot ROM Loader: Protocols and Interfacing Topic Page C.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 C.2 Protocol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Introduction C.1 Introduction The ’240x Digital Signal Processors (DSPs) contain an on-chip read-only memory (ROM) containing bootloader code. This code loads code from an external serial boot device at reset, and transfers control to the code loaded from the external device. This chapter describes working with this feature of the device. The ’240x device Boot ROM offers the user two options—it can load code through either asynchronous or synchronous serial transfer.
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Introduction It is suggested that this pin should be driven via a resistor as well, since if the SPI is used at any time during the operation of the system, SPISIMO will be an output. 4) Destination check. The incoming destination is now compared to FE00h to FFFFh. If the destination matches this range, the CNF bit (Bit 12) in the status register ST1 is set, configuring the DARAM memory block B0 to Program Memory Space.
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Introduction Figure C–1.
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Introduction Figure C–2.
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Protocol Definitions C.2 Protocol Definitions The transfer of data is done according to a defined protocol for the SPI and SCI. The protocol for the synchronous transfer over the SPI is discussed in section C.2.1, and the protocol for the SCI transfer is discussed in section C.2.2. C.2.1 SPI Synchronous Transfer Protocol and Data Formats The ROM loader expects an 8-bit-wide SPI-compatible EEPROM device to be present on the SPI pins as indicated in Figure C–1.
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Protocol Definitions Figure C–3. SPI Data Packet Definition Byte0:Byte1 Destination Byte2:Byte3 Length (n) Byte4:Byte5 Opcode 0 Byte6:Byte7 Opcode 1 • • • Opcode n–1 C.2.2 SCI Asynchronous Transfer Protocol and Data Formats The SCI-based loader operation is more involved than the SPI-based loader operation. The SCI-based loader incorporates a mechanism for baud-rate matching. Once the baud rate from the host is matched, the SCI loader commences the transfer. Section C.2.2.
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Protocol Definitions Table C–1. Clock Speeds at Which Baud Rate Locks CLKOUT (MHz) CLKIN (MHz) 30 7.5 28 7.0 24 6.0 20 5.0 16 4.0 C.2.2.2 Data Transfer Once the communications are synchronized, the actual data transfer is commenced. The first two bytes fetched are interpreted as the destination. The next two bytes fetched are the length. Once the destination is known, a check is performed to see if the destination lies within B0.
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Protocol Definitions Figure C–4.
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Protocol Definitions Figure C–5.
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Protocol Definitions Figure C–6.
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Protocol Definitions ;***************************************************************************** ; File Name: BOOT.asm ; Originator: Digital Control Systems Group, ; Texas Instruments ;***************************************************************************** ; Constant definitions ;***************************************************************************** READ_COMMAND .set 0300H ;Serial EEPROM Read Command in HByte VBR_MAX .set 09h ;# times valid char needs to be received CRC_MAX .
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Protocol Definitions LDP .endm #0E0h ;***************************************************************************** ; M A I N C O D E – starts here ;***************************************************************************** .text START: LDP #WDCR>>7 SPLK #0060h,SCSR ;CLKOUT=CPUCLK SELECT_LOADER: LDP SPLK #PCDATDIR>>7 #0000H,PCDATDIR LACC AND PCDATDIR #0004H BCND SCI_LOADER,EQ ;if IOPC2 is low, branch to SCI load ;else SPI loader and set SPISTE high. SETC XF ;Drive (!CS=XF) High.
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Protocol Definitions ;***************************************************************************** CALL GET_WORD ;Get word Sends two zero chars ;i.e. Top address in EEPROM ;***************************************************************************** ;Ok, now do two word transfers and get the two words for ;(DEST)ination and (LENGTH) of code to be boot–loaded.
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Protocol Definitions ;***************************************************************************** ; ;G E T _ W O R D ; ;This routine gets a word from the EEPROM and packs it. ;It’s returned in the accumulator ; ; ; ;Exit Conditions: ; 1. DP is set to B1 on Exit. ; 2. ACC,GPR0 are destroyed. ; 3. Result returned in ACC ; 4. Doesnt care about DP on enter.
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Protocol Definitions ;Initialisation ;***************************************************************************** SCI_LOADER: UART_INIT: ;***************************************************************************** ;SCI Initialization ;***************************************************************************** SCI_INIT: LDP #OCRA>>7 LACC OCRA ; Set up pins as SCI pins.
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Protocol Definitions INC_VBRC POINT_B1 LACC VBR_CNTR ADD #1h SACL VBR_CNTR SUB #VBR_MAX POINT_PF1 BCND UI01, NEQ SND_ECHO LACC SACL B BAUD_RETRY POINT_B1 SPLK #0h, VBR_CNTR LACC CHAR_RETRY_CNTR ADD #1h SACL CHAR_RETRY_CNTR SUB #CRC_MAX BCND INC_TBL_PTR,GEQ POINT_PF1 B UI01 INC_TBL_PTR LACC ADD AND SACL SPLK B #0Aah SCITXBUF BAUD_DETECTED ;Inc VBR counter ;Is VBR counter > max value ? ;No! fetch another char ;Yes! ;Indicate Host Baudrate lock ;Inc CRC counter ;Is CRC > max value ? ;Yes! try next
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Protocol Definitions ;***************************************************************************** ; Routine Name: X F E R _ S C I _ 2 _ P R O G Routine Type: SR ;***************************************************************************** XFER_SCI_2_PROG: MAR *, AR0 LAR AR0, LENGTH LACC DEST ;ACC=dest address XSP0 CALL TBLW ADD BANZ RET FETCH_SCI_WORD data_buf #01h XSP0 ;data_buff––>[*ACC] ;ACC++ ;loop ”length” times ;***************************************************************************** ; Ro
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Protocol Definitions CHK_DST_EXIT: AND BCND SETC RET #0FFFFH ;mask bits in Acc High. CHK_DST_EXIT,NEQ CNF ;***************************************************************************** KICK_DOG: SPLK #05555h, WDKEY SPLK #0AAAAh, WDKEY RET ;***************************************************************************** ; Table of SCI_LBAUD Contents. ;***************************************************************************** ; SCI_LBAUD @38.
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Appendix AppendixDA Glossary A A0–A15: Collectively, the external address bus; the 16 pins are used in parallel to address external data memory, program memory, or I/O space. ACC: See accumulator. ACCH: Accumulator high word. The upper 16 bits of the accumulator. See also accumulator. ACCL: Accumulator low word. The lower 16 bits of the accumulator. See also accumulator.
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Glossary auxiliary register arithmetic unit (ARAU): A 16-bit arithmetic unit used to increment, decrement, or compare the contents of the auxiliary registers. Its primary function is manipulating auxiliary register values for indirect addressing. auxiliary register pointer (ARP): A 3-bit field in status register ST0 that points to the current auxiliary register.
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Glossary C C bit: See carry bit. CALU: See central arithmetic logic unit (CALU). carry bit: Bit 9 of status register ST1; used by the CALU for extended arithmetic operations and accumulator shifts and rotates. The carry bit can be tested by conditional instructions. central arithmetic logic unit (CALU): The 32-bit wide main arithmetic logic unit for the ’24x CPU that performs arithmetic and logic operations. It accepts 32-bit values for operations, and its 32-bit output is held in the accumulator.
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Glossary CPU cycle: The time required for the CPU to go through one logic phase (during which internal values are changed) and one latch phase (during which the values are held constant). current AR: See current auxiliary register. current auxiliary register: The auxiliary register pointed to by the auxiliary register pointer (ARP). The auxiliary registers are AR0 (ARP = 0) through AR7 (ARP = 7). See also auxiliary register; next auxiliary register.
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Glossary data read bus (DRDB): A 16-bit internal bus that carries data from data memory to the CALU and the ARAU. data-write address bus (DWAB): A 16-bit internal bus that carries the address for each write to data memory. data write bus (DWEB): A 16-bit internal bus that carries data to both program memory and data memory. decode phase: The phase of the pipeline in which the instruction is decoded. See also pipeline; instruction-fetch phase; operand-fetch phase; instruction-execute phase.
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Glossary F FIFO buffer: First-in, first-out buffer. A portion of memory in which data is stored and then retrieved in the same order in which it was stored. The synchronous serial port has two four-word-deep FIFO buffers: one for its transmit operation and one for its receive operation. flash memory: Electrically erasable and programmable, nonvolatile (readonly) memory. G general-purpose input/output pins: Pins that can be used to accept input signals or send output signals.
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Glossary instruction-decode phase: The second phase of the pipeline; the phase in which the instruction is decoded. See also pipeline; instruction-fetch phase; operand-fetch phase; instruction-execute phase. instruction-execute phase: The fourth phase of the pipeline; the phase in which the instruction is executed. See also pipeline; instruction-fetch phase; instruction-decode phase; operand-fetch phase.
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Glossary interrupt vector: A branch instruction that leads the CPU to an interrupt service routine (ISR). interrupt vector location: An address in program memory where an interrupt vector resides. When an interrupt is acknowledged, the CPU branches to the interrupt vector location and fetches the interrupt vector. INTM bit: See interrupt mode bit (INTM). I/O-mapped register: One of the on-chip registers mapped to addresses in I/O (input/output) space.
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Glossary master clock output signal: See CLKOUT1. master phase: See logic phase. memory-mapped register: One of the on-chip registers mapped to addresses in data memory. See also I/O-mapped register. microcontroller mode: A mode in which the on-chip ROM or flash memory in program memory space is enabled. This mode is selected with the MP/ MC pin. microprocessor mode: A mode in which the on-chip ROM or flash memory is disabled and external program memory is enabled. This mode is selected with the MP/MC pin.
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Glossary nonmaskable interrupt: An interrupt that can be neither masked by the interrupt mask register (IMR) nor disabled by the INTM bit of status register ST0. NPAR: Next program address register. Part of the program-address generation logic. This register provides the address of the next instruction to the program counter (PC), the program address register (PAR), the micro stack (MSTACK), or the stack. O operand: A value to be used or manipulated by an instruction; specified in the instruction.
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Glossary PC: See program counter (PC). PCB: Printed circuit board. pending interrupt: A maskable interrupt that has been successfully requested but is awaiting acknowledgement by the CPU. pipeline: A method of executing instructions in an assembly line fashion. The ’24x pipeline has four independent phases. During a given CPU cycle, four different instructions can be active, each at a different stage of completion.
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Glossary program control logic: Logic circuitry that decodes instructions, manages the pipeline, stores status of operations, and decodes conditional operations. program counter (PC): A register that indicates the location of the next instruction to be executed. program read bus (PRDB): A 16-bit internal bus that carries instruction code and immediate operands, as well as table information, from program memory to the CPU. PS: Program select pin.
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Glossary RPTC: See repeat counter (RPTC). RS: Reset pin. When driven low, causes a reset on any ’24x device. R/W: Read/write pin. Indicates the direction of transfer between the ’24x and external program, data, or I/O space. S scratch-pad RAM: Another name for DARAM block B2 in data space (32 words). short-immediate value: An 8-, 9-, or 13-bit constant given as an operand of an instruction that is using immediate addressing.
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Glossary STRB: External access active strobe. The ’24x asserts STRB during accesses to external program, data, or I/O space. SXM bit: See sign-extension mode bit (SXM). T TC bit: Test/control flag bit. Bit 11 of status register ST1; stores the results of test operations done in the central arithmetic logic unit (CALU) or the auxiliary register arithmetic unit (ARAU). The TC bit can be tested by conditional instructions.
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Glossary XF pin: External flag pin. A general-purpose output pin whose status can be read or changed by way of the XF bit in status register ST1. XINT1–XINT2: External pins used to generate general-purpose hardware interrupts. Z zero fill: A way to fill the unused low or high order bits in a register by inserting 0s.
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Index Index addressing modes, definition D-1 architecture, summary 2-2 auxiliary register pointer (ARP) D-2 auxiliary register pointer buffer (ARB) A AAn (abort acknowledge) acceptance filter 10-16 10-19 accumulator, definition D-1 ACQ (acquisition time) 7-34 B ACTR, compare action control register 6-42 ADC (analog to digital converter) ADC control register 1 (ADCTRL1) 7-20 ADC control register 2 (ADCTRL2) 7-23 autoconversion sequencer 7-4 autosequence status register (AUTO_SEQ_SR) 7-29 autosequenced
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Index interrupt logic 10-32 introduction 10-2 local acceptance mask (LAM) 10-16 local acceptance mask register n (0,1) high word (LAMn_H), figure 10-17 local acceptance mask register n (0,1) low word (LAMn_L), figure 10-17 mailbox addresses 10-8 mailbox configuration details, table 10-5 mailbox direction enable register (MDER), figure 10-18 mailbox layout 10-10 mailbox RAM 10-10 write access 10-12 mailboxes receive 10-13 transmit 10-13 master control register (MCR), figure 10-22 memory map 10-6 message buf
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Index CAN data frame 10-4 CAN error counter register (CEC), figure 10-31 CAN initialization, figure 10-36 CAN interrupt flag register (CAN_IFR), figure 10-33 CAN interrupt mask register (CAN_IMR), figure 10-35 CAN notation, table 10-39 power-down mode 10-37 CAN protocol overview 10-3 configuration mode 10-36 control registers 10-18 error status register (ESR), figure 10-29 global status register (GSR), figure 10-28 interrupt logic 10-32 introduction 10-2 local accepance mask (LAM) 10-16 local acceptance ma
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Index capture FIFO status register (CAPFIFO) 6-73 capture units, features 6-68 compare unit interrupts 6-45 compare unit registers 6-39 compare action control register (ACTR) 6-42 compare control register (COMCON) 6-39 compare unit reset 6-45 compare units 6-37 compare inputs/outputs 6-38 compare operation modes 6-38 operation 6-38 register setup for compare unit operation 6-39 comparison to ’C240 EV 6-5 EV2 interrupt flag registers 6-85 EV2 interrupt flag register A 6-85 EV2 interrupt flag register B 6-87
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Index QEP decoding 6-79 QEP circuit 6-79 QEP decoding example 6-80 QEP pins 6-78 quadrature encoder pulse (QEP) circuit 6-78 register addresses 6-11, 6-13 register setup for PWM generation 6-56 register setup for QEP circuits 6-80 registers 6-9 space vector PWM 6-60 3–phase power inverter 6-60 approximating motor voltage with basic space vectors 6-62 power inverter switching patterns and basic space vectors 6-60 space vector PWM boundary conditions 6-64 space vector PWM waveform generation with event manag
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Index peripheral interrupt request descriptions (PIRQR1) 2-30, 2-31, 2-34 peripheral interrupt request descriptions (PIRQR0) 2-28 interrupt acknowledge 2-15 interrupt flag register (IFR) 2-23 to 2-38 interrupt latency, definition D-7 interrupt mask register (IMR) 2-25 to 2-38 interrupt priority and vectors 2-8 interrupt request structure 2-14 interrupt service routines (ISRs), definition D-7 interrupt vectors 2-16 phantom interrupt vector 2-17 interrupts IMR register 2-25 interrupt mask register 2-25 maski
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Index off-chip memory, configuration, local data 3-15 on-chip memory advantages 3-3 configuration 3-15 OPCn (overwrite protection control) 10-22 overview, TMS320 family 1-2 P PADATDIR, port A data and direction control register 5-9 PAR (program address register), definition D-10 PARITY ENABLE bit 2-24, 2-25, 2-26 PBDATDIR, port B data and direction control register 5-11 PCDATDIR, port C data and direction control register 5-12 PDDATDIR port D data and direction control register 5-13 port D data and direct
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Index port C data and direction control register (PCDATDIR) 5-12 port C data and direction control register (PDDATDIR), for ’C242 only 5-13 port D data and direction control register (PDDATDIR), for ’X241 and ’X243 5-14 XINT1 control register (XINT1CR) 2-36 XINT2 control register (XINT2CR) 2-37 remote frames 10-14 remote requests receiving 10-14 sending 10-15 reset 2-35, 4-4 RFPn (remote frame pending register) RMLn (receive message lost) 10-21 10-21 RMPn (receive message pending) 10-22 ROM, facto
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Index SPI operation 9-6 introduction to operation 9-6 master mode 9-7 slave mode 9-8 SPI master/slave connection 9-7 SPI physical description 9-2 software hierarchy 2-18 SOS_synch, start of sequence sync-up) 7-34 SPI, serial peripheral interface 9-1 stop bits (1 or 2) 2-24, 2-25 T TAn (transmission acknowledge) 10-19 TCR (transmission control register), figure 10-19 TMS320 family 1-2 to 1-6 advantages 1-2 development 1-2 history 1-2 overview 1-2 transmit mailboxes 10-13 TRRn (transmission request reset) 1