Specification Sheet
Table Of Contents
- About the Document
- Contents
- Table Index
- Figure Index
- 1 Introduction
- 2 Product Concept
- 3 Application Interface
- 4 Electrical and Radio Characteristics
- 5 Dimensions and Packaging
- 6 Appendix References
LTE Module Series
EC25 Mini PCIe Hardware Design
EC25_Mini_PCIe_Hardware_Design Confidential / Released 23 / 42
In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge. The PCM_SYNC falling edge represents the MSB. In this mode, PCM_CLK supports 128, 256, 512,
1024 and 2048kHz for different speed codecs. The following figure shows the timing relationship in
primary mode with 8kHz PCM_SYNC and 2048kHz PCM_CLK.
PCM_CLK
PCM_SYNC
PCM_DOUT
MSB
LSB
MSB
125us
1 2 256255
PCM_DIN
MSB
LSBMSB
Figure 6: Timing in Primary Mode
In auxiliary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge; while the PCM_SYNC rising edge represents the MSB. In this mode, PCM interface operates with a
128kHz PCM_CLK and an 8kHz, 50% duty cycle PCM_SYNC only. The following figure shows the timing
relationship in auxiliary mode with 8kHz PCM_SYNC and 128kHz PCM_CLK.
PCM_CLK
PCM_SYNC
PCM_DOUT
MSB
LSB
PCM_DIN
125us
MSB
1 2 1615
LSB
Figure 7: Timing in Auxiliary Mode
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