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SM646UDR26485-2-I

January 31, 2006

Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com

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Asia/Pacific: Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903

Ordering Information

Part Numbers Description Device Vendor

SM646UDR26485-2-I 64Mx64 (512MB), DDR2, 240-pin DIMM, Unbuffered,

Non-ECC, 64Mx8 Based, PC2-5300, DDR2-667-555,

30.00mm, 22Ω DQ termination.

Infineon, Rev. A

HYB18T512800AF-3S

Summary of content (25 pages)

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SM646UDR26485-2-I January 31, 2006 Ordering Information Part Numbers Description Device Vendor SM646UDR26485-2-I 64Mx64 (512MB), DDR2, 240-pin DIMM, Unbuffered, Non-ECC, 64Mx8 Based, PC2-5300, DDR2-667-555, 30.00mm, 22Ω DQ termination. Infineon, Rev. A HYB18T512800AF-3S Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.
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SM646UDR26485-2-I January 31, 2006 Revision History • January 31, 2006 Corrected the OCD Program in the EMRS on page 14. • October 4, 2005 Datasheet released. Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.
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SM646UDR26485-2-I January 31, 2006 512MByte (64Mx64) DDR2 SDRAM Module - 64Mx8 Based 240-pin DIMM, Unbuffered, Non-ECC Features • • • • • • • • Standard Configuration Cycle Time CAS# Latency Posted CAS#/Additive Latency (AL) Write Latency (WL) Burst Length Burst Type : : : : JEDEC ECC 3.0ns 3.0, 4.0, 5.0 : : : : 0, 1.0, 2.0, 3.0 & 4.0 Read (CAS#) Latency - 1 4, 8 Sequential/Interleave • • • • • • • • No. of Internal Banks per SDRAM : 4 Operating Voltage : 1.
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SM646UDR26485-2-I January 31, 2006 240-pin DDR2 DIMM Pin List (Contd.) Pin Pin No. Name Pin Pin No. Name Pin Pin No. Name Pin Pin No. Name Pin Pin No. Name Pin Pin No. Name Pin Pin No. Name 21 DQ10 51 VDDQ 81 DQ33 111 DQ57 141 DQ15 171 CKE1 (NC) 201 VSS Pin Pin No.
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SM646UDR26485-2-I January 31, 2006 Pin Description Table (Contd.) Symbol Type Polarity Function A0~A9, A10/AP, A11~A13 SSTL_18 - During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled at the rising clock edge. In addition to the column address, A10/AP is used to invoke autoprecharge operation at the end of the burst read or write cycle.
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SM646UDR26485-2-I January 31, 2006 Block Diagram CS0# CKE0 ODT0 DQS0 DQS0# DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 S# CKE ODT DQS DQS# DM I/O 0 I/O 1 D0 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS4 DQS4# DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 S# CKE ODT DQS DQS# DM I/O 0 I/O 1 D4 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS1 DQS1# DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 S# CKE ODT DQS DQS# DM I/O 0 I/O 1 D1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS5 DQS5# DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 S# CKE O
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SM646UDR26485-2-I January 31, 2006 5.
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SM646UDR26485-2-I January 31, 2006 Physical Dimensions 240-pin DIMM Module 2.57 (max.) 64 1 65 120 55.00 63.00 5.175 10.00 4.00 (min.) 19.80 17.80 30.00 133.35±0.15 5.175 1.27±0.10 Detail A Detail B Detail C Front View 3.00 4x FULL R 4x 5.00 4.00 4x FULL R 65 64 3.80 1.50±0.10 2.50 Detail A 0.20±0.15 2.50±0.20 1.00 0.80±0.05 Detail B 1.00 4x Detail C ( All dimensions are in millimeters with ±0.15mm tolerance unless specified otherwise.) Corporate Headquarters: P. O.
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SM646UDR26485-2-I January 31, 2006 Serial Presence Detect Table Byte No. Byte Description Value Supported Value in Hex 0 # of bytes written into serial memory at module manufacturer 128 Bytes 80h 1 Total # of bytes of SPD memory device 256 Bytes 08h 2 Fundamental memory type SDRAM DDR2 08h 3 # of row address on this assembly 14 0Eh 4 # of column address on this assembly 10 0Ah 5 # of Ranks, Package and Height 1, Planar, 30.
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SM646UDR26485-2-I January 31, 2006 Serial Presence Detect Table (Contd.) Byte No. Byte Description Value Supported Value in Hex 27 Minimum row precharge time (=tRP) 15ns 3Ch 28 Minimum row active to row active delay (=tRRD) 7.5ns 1Eh 29 Minimum RAS to CAS delay (=tRCD) 15ns 3Ch 30 Minimum activate precharge time (=tRAS) 45ns 2Dh 31 Module row density 512MB 80h 32 Command and Address signal input setup time 0.20ns 20h 33 Command and Address signal input hold time 0.
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SM646UDR26485-2-I January 31, 2006 Serial Presence Detect Table (Contd.) Byte No. Byte Description Value Supported Value in Hex 53 ∆T3P.fast (DT3P fast) 2.15°C 2Bh 54 ∆T3P.slow (DT3P slow) 0.675°C 1Bh 55 ∆T4R (DT4R) / ∆T4R4W S Sign (DT4R4W) 14.
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SM646UDR26485-2-I January 31, 2006 Mode Register Table Definition The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode register must be written after powerup for proper operation.
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SM646UDR26485-2-I January 31, 2006 Extended Mode Register Table Definition The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/ disable, output drive strength, ODT (RTT), Posted CAS additive latency (AL), off-chip driver impedance calibration (OCD), DQS# enable/disable, RDQS/RDQS# enable/disable, and OUTPUT enable/disable.
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SM646UDR26485-2-I January 31, 2006 Extended Mode Register Table BA2 BA1 BA0 A15~A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field E18 E17 E16 E15~E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 Extended Mode Register 01 0 Qoff RDQS DQS# RTT D.I.
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SM646UDR26485-2-I January 31, 2006 Commands The following Truth Tables provide a general reference of available commands. For a more detailed description please refer to the device data sheets.
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SM646UDR26485-2-I January 31, 2006 DC Characteristics Absolute Maximum Ratings Parameter Symbol Ratings Unit VDD -1.0 ~ 2.3 V Voltage on VDDQ relative to VSS VDDQ -0.5 ~ 2.3 V Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 2.3 V Voltage on VDDSPD relative to VSS VDDSPD 1.7 ~ 3.6 V Operating Temperature (Ambient) TOPR 0 to +65 °C Operating Temperature (Case) TCASE 0 to +95 °C TSTG -55 to +100 °C Voltage on VDD relative to VSS Storage Temperature Notes 1, 2 Notes: 1.
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SM646UDR26485-2-I January 31, 2006 Capacitance (VDD = 1.8V±0.1V, TCase = +25°C) Parameter Symbol Min Max Unit CCK 3.0 6.0 pF CDCK - 0.75 pF CI 8.0 16.0 pF Input Capacitance delta (all other input-only pins) CDI - 2.0 pF Input/Output Capacitance (DQ, DM, DQS, DQS#) CI0 2.5 3.5 pF CDI0 - 0.
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SM646UDR26485-2-I January 31, 2006 ODT DC Electrical Characteristics Parameter Symbol Min Nom Max Unit Notes RTT effective impedence value for 75Ω setting EMR (A6, A2) = 0, 1 RTT1(EFF) 60 75 90 Ω 1 RTT effective impedence value for 150Ω setting EMR (A6, A2) = 1, 0 RTT2(EFF) 120 150 180 Ω 1 RTT effective impedence value for 50Ω setting EMR (A6, A2) = 1, 1 RTT3(EFF) 40 50 60 Ω 1 Deviation of VM with respect to VDDQ/2 ∆VM -6 +6 % 2 Notes: 1.
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SM646UDR26485-2-I January 31, 2006 OCD Default Output Characteristics (VDD = 1.8V±0.1V, VSS = 0V, TA = 0 to +65°C) Parameter Symbol Output Impedance Pull-up and Pull-down mismatch Output Slew Rate SOUT Output Step Size for Calibration Min Nom Max Unit Notes 12.6 18 23.4 Ω 1, 2 0 4 Ω 1, 2, 3 1.5 5 V/ns 0 1.5 Ω 1, 4, 5, 7 6 Notes: 1. Absolute specifications: 0°C ≤ Tcase ≤ +85°C; VDDQ = +1.8V±0.1V, VDD = +1.8V±0.1V. 2.
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SM646UDR26485-2-I January 31, 2006 IDD Specification Parameters and Test Conditions (VDD = 1.8V±0.1V, VSS = 0V, TA = 0 to +65°C) 3.0ns CL 5.
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SM646UDR26485-2-I January 31, 2006 IDD Specification Parameters and Test Conditions (Contd.) Notes: 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate is specified by AC Parametric Test Condition. 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS#. IDD values must be met with all combinations of ERMS bits 10 and 11. 5.
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SM646UDR26485-2-I January 31, 2006 Device AC Operating Conditions Parameter 3.0ns @ CL 5.0 DDR2-667 Symbol Min Clock cycle time CL=5.0 tCK CL=4.0 CL=3.0 Unit Notes Max 3000 8000 ps 12, 20 3750 8000 ps 12, 20 5000 8000 ps 12, 20 Clock high-level width tCH 0.45 0.55 t CK 14 Clock low-level width tCL 0.45 0.
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SM646UDR26485-2-I January 31, 2006 Device AC Operating Conditions (Contd.) Parameter 3.0ns @ CL5.0 DDR2-667 Symbol Min Unit Notes 24 Max CKE low to CK,CK# uncertainity tDELAY 3.475 3.475 ns ACTIVE to ACTIVE (same bank) command tRC 60 - ns ACTIVE bank a to ACTIVE bank b command tRRD 7.5 - ns ACTIVE to READ or WRITE delay tRCD 15 - ns ACTIVE to PRECHARGE command tRAS 45 70000 ns 16 Internal READ to precharge command delay tRTP 7.
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SM646UDR26485-2-I January 31, 2006 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. The AC and DC input level specifications are as defined in the SSTL_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level. Command/Address minimum input slew rate = 1.
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SM646UDR26485-2-I January 31, 2006 Disclaimer: No part of this document may be copied or reproduced in any form or by any means, or transferred to any third party, without the prior written consent of an authorized representative of SMART Modular Technologies, Inc. (“SMART”). The information in this document is subject to change without notice.